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| author | Roger Ferrer Ibanez <rofirrim@gmail.com> | 2019-09-30 07:58:50 +0000 |
|---|---|---|
| committer | Roger Ferrer Ibanez <rofirrim@gmail.com> | 2019-09-30 07:58:50 +0000 |
| commit | 5a2a14db0bc4cfd4f3c8f2fbac7ca9bc93a23699 (patch) | |
| tree | 1821e5f188ac602b3120d6f5925ccded2c835c4d /llvm/test/CodeGen/RISCV/arith-with-overflow.ll | |
| parent | b3438f1cc040ec37ca437ce48b6373298b4ecf9a (diff) | |
| download | bcm5719-llvm-5a2a14db0bc4cfd4f3c8f2fbac7ca9bc93a23699.tar.gz bcm5719-llvm-5a2a14db0bc4cfd4f3c8f2fbac7ca9bc93a23699.zip | |
[TargetLowering] Simplify expansion of S{ADD,SUB}O
ISD::SADDO uses the suggested sequence described in the section ยง2.4 of
the RISCV Spec v2.2. ISD::SSUBO uses the dual approach but checking for
(non-zero) positive.
Differential Revision: https://reviews.llvm.org/D47927
llvm-svn: 373187
Diffstat (limited to 'llvm/test/CodeGen/RISCV/arith-with-overflow.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/arith-with-overflow.ll | 28 |
1 files changed, 8 insertions, 20 deletions
diff --git a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll index 8d720824119..4358fb5a1b8 100644 --- a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll +++ b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll @@ -10,17 +10,11 @@ declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b) define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: sadd: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: addi a3, zero, -1 -; RV32I-NEXT: slt a4, a3, a1 -; RV32I-NEXT: slt a5, a3, a0 -; RV32I-NEXT: xor a4, a5, a4 -; RV32I-NEXT: seqz a4, a4 -; RV32I-NEXT: add a1, a0, a1 -; RV32I-NEXT: slt a0, a3, a1 -; RV32I-NEXT: xor a0, a5, a0 -; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: and a0, a4, a0 -; RV32I-NEXT: sw a1, 0(a2) +; RV32I-NEXT: add a3, a0, a1 +; RV32I-NEXT: slt a0, a3, a0 +; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: sw a3, 0(a2) ; RV32I-NEXT: ret entry: %x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) @@ -33,16 +27,10 @@ entry: define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind { ; RV32I-LABEL: ssub: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: addi a3, zero, -1 -; RV32I-NEXT: slt a4, a3, a1 -; RV32I-NEXT: slt a5, a3, a0 -; RV32I-NEXT: xor a4, a5, a4 -; RV32I-NEXT: snez a4, a4 +; RV32I-NEXT: sgtz a3, a1 ; RV32I-NEXT: sub a1, a0, a1 -; RV32I-NEXT: slt a0, a3, a1 -; RV32I-NEXT: xor a0, a5, a0 -; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: and a0, a4, a0 +; RV32I-NEXT: slt a0, a1, a0 +; RV32I-NEXT: xor a0, a3, a0 ; RV32I-NEXT: sw a1, 0(a2) ; RV32I-NEXT: ret entry: |
