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authorRafael Espindola <rafael.espindola@gmail.com>2013-06-05 01:48:30 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2013-06-05 01:48:30 +0000
commitbeef23fe2117d0d66c28bc9b48df285a882c026d (patch)
tree97f4f14abe586a2a4320d3f1e30044883a21c2ae /llvm/test/CodeGen/R600/texture-input-merge.ll
parente699c60021c6ee9499ed7292e9b905e7b772377d (diff)
downloadbcm5719-llvm-beef23fe2117d0d66c28bc9b48df285a882c026d.tar.gz
bcm5719-llvm-beef23fe2117d0d66c28bc9b48df285a882c026d.zip
Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. llvm-svn: 183286
Diffstat (limited to 'llvm/test/CodeGen/R600/texture-input-merge.ll')
-rw-r--r--llvm/test/CodeGen/R600/texture-input-merge.ll30
1 files changed, 0 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/R600/texture-input-merge.ll b/llvm/test/CodeGen/R600/texture-input-merge.ll
deleted file mode 100644
index 5d0ecef3069..00000000000
--- a/llvm/test/CodeGen/R600/texture-input-merge.ll
+++ /dev/null
@@ -1,30 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK-NOT: MOV
-
-define void @test() {
- %1 = call float @llvm.R600.load.input(i32 0)
- %2 = call float @llvm.R600.load.input(i32 1)
- %3 = call float @llvm.R600.load.input(i32 2)
- %4 = call float @llvm.R600.load.input(i32 3)
- %5 = fmul float %1, 3.0
- %6 = fmul float %2, 3.0
- %7 = fmul float %3, 3.0
- %8 = fmul float %4, 3.0
- %9 = insertelement <4 x float> undef, float %5, i32 0
- %10 = insertelement <4 x float> %9, float %6, i32 1
- %11 = insertelement <4 x float> undef, float %7, i32 0
- %12 = insertelement <4 x float> %11, float %5, i32 1
- %13 = insertelement <4 x float> undef, float %8, i32 0
- %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- %17 = fadd <4 x float> %14, %15
- %18 = fadd <4 x float> %17, %16
- call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
- ret void
-}
-
-declare float @llvm.R600.load.input(i32) readnone
-declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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