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| author | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:46 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:46 +0000 |
| commit | 7e2c83256bb55fcd634b055d72755f7724e89c54 (patch) | |
| tree | a30c0c21b017b7fc4b592de6cb6b253411b5f88b /llvm/test/CodeGen/R600/store.ll | |
| parent | 4d5c5e53d0f79185b30888dc809b6ca69645d718 (diff) | |
| download | bcm5719-llvm-7e2c83256bb55fcd634b055d72755f7724e89c54.tar.gz bcm5719-llvm-7e2c83256bb55fcd634b055d72755f7724e89c54.zip | |
R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
Diffstat (limited to 'llvm/test/CodeGen/R600/store.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/store.ll | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/llvm/test/CodeGen/R600/store.ll b/llvm/test/CodeGen/R600/store.ll index 2609dab422f..341c42791a1 100644 --- a/llvm/test/CodeGen/R600/store.ll +++ b/llvm/test/CodeGen/R600/store.ll @@ -10,15 +10,15 @@ ; EG-CHECK: @store_i8 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]] -; IG 0: Get the byte index -; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; IG 0: Get the byte index and truncate the value +; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-CHECK-NEXT: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y +; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43) +; IG 1: Truncate the calculated the shift amount for the mask +; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x ; EG-CHECK-NEXT: 3 -; IG 1: Truncate the value and calculated the shift amount for the mask -; EG-CHECK: AND_INT T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.x -; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.y -; EG-CHECK: 255(3.573311e-43), 3 ; IG 2: Shift the value and the mask -; EG-CHECK: LSHL T[[RW_GPR]].X, PV.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] +; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] ; EG-CHECK-NEXT: 255 ; IG 3: Initialize the Y and Z channels to zero @@ -39,15 +39,15 @@ entry: ; EG-CHECK: @store_i16 ; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]] -; IG 0: Get the byte index -; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-CHECK-NEXT: 3 -; IG 1: Truncate the value and calculated the shift amount for the mask -; EG-CHECK: AND_INT T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.x -; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.y -; EG-CHECK: 65535(9.183409e-41), 3 +; IG 0: Get the byte index and truncate the value +; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y +; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41) +; IG 1: Truncate the calculated the shift amount for the mask +; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG-CHECK: 3 ; IG 2: Shift the value and the mask -; EG-CHECK: LSHL T[[RW_GPR]].X, PV.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] +; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] ; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] ; EG-CHECK-NEXT: 65535 ; IG 3: Initialize the Y and Z channels to zero |
