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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-23 01:48:35 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-23 01:48:35 +0000 |
| commit | 9f95033d3345bd7a86a5e132fafd72d51e30eef9 (patch) | |
| tree | e51b4d6065c155b88a538e4d3c344cdd30eef594 /llvm/test/CodeGen/R600/short-args.ll | |
| parent | ba30932908ab09f5bb9fa33ba793816e2b1ea398 (diff) | |
| download | bcm5719-llvm-9f95033d3345bd7a86a5e132fafd72d51e30eef9.tar.gz bcm5719-llvm-9f95033d3345bd7a86a5e132fafd72d51e30eef9.zip | |
R600: Improve support for < 32-bit loads
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186921
Diffstat (limited to 'llvm/test/CodeGen/R600/short-args.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/short-args.ll | 36 |
1 files changed, 22 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/R600/short-args.ll b/llvm/test/CodeGen/R600/short-args.ll index 69a8412c88e..20d0ae43c9d 100644 --- a/llvm/test/CodeGen/R600/short-args.ll +++ b/llvm/test/CodeGen/R600/short-args.ll @@ -1,8 +1,10 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @i8_arg -; CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; EG-CHECK: @i8_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: BUFFER_LOAD_UBYTE define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { entry: @@ -11,8 +13,9 @@ entry: ret void } -; CHECK: @i8_zext_arg -; CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; EG-CHECK: @i8_zext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11 define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { entry: @@ -21,8 +24,10 @@ entry: ret void } -; CHECK: @i8_sext_arg -; CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; EG-CHECK: @i8_sext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11 + define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { entry: %0 = sext i8 %in to i32 @@ -30,8 +35,9 @@ entry: ret void } -; CHECK: @i16_arg -; CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; EG-CHECK: @i16_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: BUFFER_LOAD_USHORT define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { entry: @@ -40,8 +46,9 @@ entry: ret void } -; CHECK: @i16_zext_arg -; CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; EG-CHECK: @i16_zext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11 define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { entry: @@ -50,8 +57,9 @@ entry: ret void } -; CHECK: @i16_sext_arg -; CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; EG-CHECK: @i16_sext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11 define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { entry: |
