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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-01-29 16:55:25 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-29 16:55:25 +0000 |
| commit | 83f0bcef7a3e96d022f8d31fd87c8363fd4f9a00 (patch) | |
| tree | f29b52cf36d73c5cdc161b00203816b987f329a5 /llvm/test/CodeGen/R600/local-atomics.ll | |
| parent | e75aa4983c8bb64f63c8742d2e3dc32c6966b74b (diff) | |
| download | bcm5719-llvm-83f0bcef7a3e96d022f8d31fd87c8363fd4f9a00.tar.gz bcm5719-llvm-83f0bcef7a3e96d022f8d31fd87c8363fd4f9a00.zip | |
R600/SI: Define a schedule model and enable the generic machine scheduler
The schedule model is not complete yet, and could be improved.
llvm-svn: 227461
Diffstat (limited to 'llvm/test/CodeGen/R600/local-atomics.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/local-atomics.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/R600/local-atomics.ll b/llvm/test/CodeGen/R600/local-atomics.ll index 16d3173f369..78d747d7e72 100644 --- a/llvm/test/CodeGen/R600/local-atomics.ll +++ b/llvm/test/CodeGen/R600/local-atomics.ll @@ -4,8 +4,8 @@ ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32: ; EG: LDS_WRXCHG_RET * -; SI: s_load_dword [[SPTR:s[0-9]+]], ; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; SI: s_load_dword [[SPTR:s[0-9]+]], ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] ; SI: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] ; SI: buffer_store_dword [[RESULT]], @@ -30,8 +30,8 @@ define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac ; XXX - Is it really necessary to load 4 into VGPR? ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32: ; EG: LDS_ADD_RET * -; SI: s_load_dword [[SPTR:s[0-9]+]], ; SI: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; SI: s_load_dword [[SPTR:s[0-9]+]], ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] ; SI: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0] ; SI: buffer_store_dword [[RESULT]], |
