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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
| commit | 0344cdfe390842fd62e73a8a0cb4eb495c355076 (patch) | |
| tree | cbee5af8711fa2a8d8b8c137fa19b415d699a24f /llvm/test/CodeGen/R600/load.vec.ll | |
| parent | 53698938a47b6ee20542a0619908932acd07f7d5 (diff) | |
| download | bcm5719-llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.tar.gz bcm5719-llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.zip | |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
Diffstat (limited to 'llvm/test/CodeGen/R600/load.vec.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/load.vec.ll | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/R600/load.vec.ll b/llvm/test/CodeGen/R600/load.vec.ll index b3d63497b6c..8cba0b6a516 100644 --- a/llvm/test/CodeGen/R600/load.vec.ll +++ b/llvm/test/CodeGen/R600/load.vec.ll @@ -3,8 +3,7 @@ ; load a v2i32 value from the global address space. ; EG-CHECK: @load_v2i32 -; EG-CHECK-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4 -; EG-CHECK-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 ; SI-CHECK: @load_v2i32 ; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}} define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { |
