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| author | Vincent Lejeune <vljn@ovi.com> | 2013-11-11 22:10:24 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-11-11 22:10:24 +0000 |
| commit | f143af3fe951e086b7c158213e6e113c73835723 (patch) | |
| tree | 899df67335f187838352bfb3cf54b5b37d80bd24 /llvm/test/CodeGen/R600/load-input-fold.ll | |
| parent | 3168ab337635b6ed5a279cd432f95dc3da17fb2c (diff) | |
| download | bcm5719-llvm-f143af3fe951e086b7c158213e6e113c73835723.tar.gz bcm5719-llvm-f143af3fe951e086b7c158213e6e113c73835723.zip | |
R600: Use function inputs to represent data stored in gpr
llvm-svn: 194425
Diffstat (limited to 'llvm/test/CodeGen/R600/load-input-fold.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/load-input-fold.ll | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/R600/load-input-fold.ll b/llvm/test/CodeGen/R600/load-input-fold.ll index aff2a6e18f7..ca86d0e3690 100644 --- a/llvm/test/CodeGen/R600/load-input-fold.ll +++ b/llvm/test/CodeGen/R600/load-input-fold.ll @@ -1,20 +1,20 @@ ;RUN: llc < %s -march=r600 -mcpu=cayman ;REQUIRES: asserts -define void @main() #0 { +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { main_body: - %0 = call float @llvm.R600.load.input(i32 4) - %1 = call float @llvm.R600.load.input(i32 5) - %2 = call float @llvm.R600.load.input(i32 6) - %3 = call float @llvm.R600.load.input(i32 7) - %4 = call float @llvm.R600.load.input(i32 8) - %5 = call float @llvm.R600.load.input(i32 9) - %6 = call float @llvm.R600.load.input(i32 10) - %7 = call float @llvm.R600.load.input(i32 11) - %8 = call float @llvm.R600.load.input(i32 12) - %9 = call float @llvm.R600.load.input(i32 13) - %10 = call float @llvm.R600.load.input(i32 14) - %11 = call float @llvm.R600.load.input(i32 15) + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = extractelement <4 x float> %reg2, i32 0 + %5 = extractelement <4 x float> %reg2, i32 1 + %6 = extractelement <4 x float> %reg2, i32 2 + %7 = extractelement <4 x float> %reg2, i32 3 + %8 = extractelement <4 x float> %reg3, i32 0 + %9 = extractelement <4 x float> %reg3, i32 1 + %10 = extractelement <4 x float> %reg3, i32 2 + %11 = extractelement <4 x float> %reg3, i32 3 %12 = load <4 x float> addrspace(8)* null %13 = extractelement <4 x float> %12, i32 0 %14 = fmul float %0, %13 @@ -96,9 +96,6 @@ main_body: } ; Function Attrs: readnone -declare float @llvm.R600.load.input(i32) #1 - -; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly |
