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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-15 20:18:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-15 20:18:31 +0000 |
| commit | e9fa3b8e6bb9a8d6d6674058c18b264cce83b026 (patch) | |
| tree | 484738461c1e4b03b182af1987892e309eb56a67 /llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll | |
| parent | 1d077749ea874e9bf71ce96f5c3426e7d549118b (diff) | |
| download | bcm5719-llvm-e9fa3b8e6bb9a8d6d6674058c18b264cce83b026.tar.gz bcm5719-llvm-e9fa3b8e6bb9a8d6d6674058c18b264cce83b026.zip | |
R600/SI: Implement less wrong f32 fdiv
Assuming single precision denormals and accurate sqrt/div are not
reported, this passes the OpenCL conformance test.
llvm-svn: 213089
Diffstat (limited to 'llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll index ca5260dc5bc..42910a99afd 100644 --- a/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll +++ b/llvm/test/CodeGen/R600/llvm.AMDGPU.rcp.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=SI -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone @@ -24,7 +25,15 @@ define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind { } ; FUNC-LABEL: @rcp_pat_f32 -; SI: V_RCP_F32_e32 +; SI-UNSAFE-NOT: V_MUL_F32 +; SI-UNSAFE: V_RCP_F32_e32 +; SI-UNSAFE-NOT: V_MUL_F32 + +; Check for surrounding multiplies the correct divide has. +; SI-SAFE: V_MUL_F32 +; SI-SAFE: V_RCP_F32_e32 +; SI-SAFE: V_MUL_F32 + define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { %rcp = fdiv float 1.0, %src store float %rcp, float addrspace(1)* %out, align 4 @@ -40,7 +49,9 @@ define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { } ; FUNC-LABEL: @rsq_rcp_pat_f32 -; SI: V_RSQ_F32_e32 +; SI-UNSAFE: V_RSQ_F32_e32 +; SI-SAFE: V_SQRT_F32_e32 +; SI-SAFE: V_RCP_F32_e32 define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { %sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone %rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone |
