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| author | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:46 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-09-04 19:53:46 +0000 |
| commit | 7e2c83256bb55fcd634b055d72755f7724e89c54 (patch) | |
| tree | a30c0c21b017b7fc4b592de6cb6b253411b5f88b /llvm/test/CodeGen/R600/fsub.ll | |
| parent | 4d5c5e53d0f79185b30888dc809b6ca69645d718 (diff) | |
| download | bcm5719-llvm-7e2c83256bb55fcd634b055d72755f7724e89c54.tar.gz bcm5719-llvm-7e2c83256bb55fcd634b055d72755f7724e89c54.zip | |
R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
Diffstat (limited to 'llvm/test/CodeGen/R600/fsub.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/fsub.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/R600/fsub.ll b/llvm/test/CodeGen/R600/fsub.ll index 1608c3aced5..850d3ee4e98 100644 --- a/llvm/test/CodeGen/R600/fsub.ll +++ b/llvm/test/CodeGen/R600/fsub.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @fsub_f32 -; R600-CHECK: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W ; SI-CHECK: @fsub_f32 ; SI-CHECK: V_SUB_F32 define void @fsub_f32(float addrspace(1)* %out, float %a, float %b) { @@ -17,8 +17,8 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) ; R600-CHECK: @fsub_v2f32 -; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z -; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y +; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z +; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y ; SI-CHECK: @fsub_v2f32 ; SI-CHECK: V_SUB_F32 ; SI-CHECK: V_SUB_F32 @@ -30,10 +30,10 @@ entry: } ; R600-CHECK: @fsub_v4f32 -; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} ; SI-CHECK: @fsub_v4f32 ; SI-CHECK: V_SUB_F32 ; SI-CHECK: V_SUB_F32 |
