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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-10 22:16:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-10 22:16:07 +0000 |
| commit | 61cc9083d030f6b419aeb4579592b72134f39246 (patch) | |
| tree | 746fbf6de6707bfb57a1d41d423aa672e6218298 /llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll | |
| parent | fe0a2e677be35728630c971a2751b5a43b980432 (diff) | |
| download | bcm5719-llvm-61cc9083d030f6b419aeb4579592b72134f39246.tar.gz bcm5719-llvm-61cc9083d030f6b419aeb4579592b72134f39246.zip | |
R600/SI: Change how DS offsets are printed
Match SC by using offset/offset0/offset1 and printing
in decimal.
llvm-svn: 219537
Diffstat (limited to 'llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll b/llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll index 672dfabe5d1..628135ee4e5 100644 --- a/llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll +++ b/llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll @@ -8,19 +8,19 @@ declare void @llvm.AMDGPU.barrier.local() #1 ; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop: ; CHECK: BB0_1: ; CHECK: V_ADD_I32_e32 [[VADDR:v[0-9]+]], -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x0 +; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]] ; SI-DAG: V_ADD_I32_e32 [[VADDR4:v[0-9]+]], 4, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR4]], 0x0 +; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR4]] ; SI-DAG: V_ADD_I32_e32 [[VADDR0x80:v[0-9]+]], 0x80, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x80]], 0x0 +; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x80]] ; SI-DAG: V_ADD_I32_e32 [[VADDR0x84:v[0-9]+]], 0x84, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x84]], 0x0 +; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x84]] ; SI-DAG: V_ADD_I32_e32 [[VADDR0x100:v[0-9]+]], 0x100, [[VADDR]] -; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x100]], 0x0 +; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR0x100]] -; CI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]], 0x0, 0x1 -; CI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]], 0x20, 0x21 -; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x100 +; CI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:0 offset1:1 +; CI-DAG: DS_READ2_B32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33 +; CI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]] offset:256 ; CHECK: S_ENDPGM define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 { entry: |
