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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
| commit | 0344cdfe390842fd62e73a8a0cb4eb495c355076 (patch) | |
| tree | cbee5af8711fa2a8d8b8c137fa19b415d699a24f /llvm/test/CodeGen/R600/build_vector.ll | |
| parent | 53698938a47b6ee20542a0619908932acd07f7d5 (diff) | |
| download | bcm5719-llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.tar.gz bcm5719-llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.zip | |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
Diffstat (limited to 'llvm/test/CodeGen/R600/build_vector.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/build_vector.ll | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/R600/build_vector.ll b/llvm/test/CodeGen/R600/build_vector.ll new file mode 100644 index 00000000000..9b738a27806 --- /dev/null +++ b/llvm/test/CodeGen/R600/build_vector.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK: @build_vector2 +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK-NOT: MOV +; SI-CHECK: @build_vector2 +; SI-CHECK-DAG: V_MOV_B32_e32 [[X:VGPR[0-9]]], 5 +; SI-CHECK-DAG: V_MOV_B32_e32 [[Y:VGPR[0-9]]], 6 +; SI-CHECK: BUFFER_STORE_DWORDX2 [[X]]_[[Y]] +define void @build_vector2 (<2 x i32> addrspace(1)* %out) { +entry: + store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK: @build_vector4 +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK-NOT: MOV +; SI-CHECK: @build_vector4 +; SI-CHECK-DAG: V_MOV_B32_e32 [[X:VGPR[0-9]]], 5 +; SI-CHECK-DAG: V_MOV_B32_e32 [[Y:VGPR[0-9]]], 6 +; SI-CHECK-DAG: V_MOV_B32_e32 [[Z:VGPR[0-9]]], 7 +; SI-CHECK-DAG: V_MOV_B32_e32 [[W:VGPR[0-9]]], 8 +; SI-CHECK: BUFFER_STORE_DWORDX4 [[X]]_[[Y]]_[[Z]]_[[W]] +define void @build_vector4 (<4 x i32> addrspace(1)* %out) { +entry: + store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out + ret void +} |
