diff options
| author | Jan Vesely <jan.vesely@rutgers.edu> | 2015-04-13 16:26:00 +0000 |
|---|---|---|
| committer | Jan Vesely <jan.vesely@rutgers.edu> | 2015-04-13 16:26:00 +0000 |
| commit | d579048464395f68ce45507f1d10204db8b36ce0 (patch) | |
| tree | ce589b58ec39103c1679e2577178eac21df03f4e /llvm/test/CodeGen/R600/add.ll | |
| parent | 29ac43c3617a74f65916844dcc98abd2f77e1059 (diff) | |
| download | bcm5719-llvm-d579048464395f68ce45507f1d10204db8b36ce0.tar.gz bcm5719-llvm-d579048464395f68ce45507f1d10204db8b36ce0.zip | |
R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO
v2: tighten the sub64 tests
v3: rename to CARRY/BORROW
v4: fixup test cmdline
add known bits computation
use sign extend instead of sub 0,x
better add test
v5: remove redundant break
move lowering to separate functions
fix comments
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewers: arsenm
llvm-svn: 234759
Diffstat (limited to 'llvm/test/CodeGen/R600/add.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/add.ll | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/R600/add.ll b/llvm/test/CodeGen/R600/add.ll index 70271616796..655e75dbc1a 100644 --- a/llvm/test/CodeGen/R600/add.ll +++ b/llvm/test/CodeGen/R600/add.ll @@ -62,6 +62,7 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ; EG: ADD_INT ; EG: ADD_INT ; EG: ADD_INT + ; SI: s_add_i32 ; SI: s_add_i32 ; SI: s_add_i32 @@ -94,6 +95,7 @@ entry: ; EG: ADD_INT ; EG: ADD_INT ; EG: ADD_INT + ; SI: s_add_i32 ; SI: s_add_i32 ; SI: s_add_i32 @@ -120,6 +122,14 @@ entry: ; FUNC-LABEL: {{^}}add64: ; SI: s_add_u32 ; SI: s_addc_u32 + +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] +; EG-DAG: ADD_INT {{[* ]*}}[[LO]] +; EG-DAG: ADDC_UINT +; EG-DAG: ADD_INT +; EG-DAG: ADD_INT {{[* ]*}}[[HI]] +; EG-NOT: SUB define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = add i64 %a, %b @@ -134,6 +144,14 @@ entry: ; FUNC-LABEL: {{^}}add64_sgpr_vgpr: ; SI-NOT: v_addc_u32_e32 s + +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] +; EG-DAG: ADD_INT {{[* ]*}}[[LO]] +; EG-DAG: ADDC_UINT +; EG-DAG: ADD_INT +; EG-DAG: ADD_INT {{[* ]*}}[[HI]] +; EG-NOT: SUB define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { entry: %0 = load i64, i64 addrspace(1)* %in @@ -146,6 +164,14 @@ entry: ; FUNC-LABEL: {{^}}add64_in_branch: ; SI: s_add_u32 ; SI: s_addc_u32 + +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] +; EG-DAG: ADD_INT {{[* ]*}}[[LO]] +; EG-DAG: ADDC_UINT +; EG-DAG: ADD_INT +; EG-DAG: ADD_INT {{[* ]*}}[[HI]] +; EG-NOT: SUB define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: %0 = icmp eq i64 %a, 0 |
