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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
| commit | 0344cdfe390842fd62e73a8a0cb4eb495c355076 (patch) | |
| tree | cbee5af8711fa2a8d8b8c137fa19b415d699a24f /llvm/test/CodeGen/R600/64bit-kernel-args.ll | |
| parent | 53698938a47b6ee20542a0619908932acd07f7d5 (diff) | |
| download | bcm5719-llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.tar.gz bcm5719-llvm-0344cdfe390842fd62e73a8a0cb4eb495c355076.zip | |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
Diffstat (limited to 'llvm/test/CodeGen/R600/64bit-kernel-args.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/64bit-kernel-args.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/R600/64bit-kernel-args.ll b/llvm/test/CodeGen/R600/64bit-kernel-args.ll index 3ad0e2ac0c4..34a0a87890c 100644 --- a/llvm/test/CodeGen/R600/64bit-kernel-args.ll +++ b/llvm/test/CodeGen/R600/64bit-kernel-args.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s --check-prefix=SI-CHECK ; SI-CHECK: @f64_kernel_arg ; SI-CHECK-DAG: S_LOAD_DWORDX2 SGPR{{[0-9]}}_SGPR{{[0-9]}}, SGPR0_SGPR1, 9 |
