[SDAG] Revert r296476 (and r296486, r296668, r296690).

This patch causes compile times for some patterns to explode. I have
a (large, unreduced) test case that slows down by more than 20x and
several test cases slow down by 2x. I'm sending some of the test cases
directly to Nirav and following up with more details in the review log,
but this should unblock anyone else hitting this.

llvm-svn: 296862

6 files changed, 111 insertions, 141 deletions

diff --git a/llvm/test/CodeGen/PowerPC/anon_aggr.ll b/llvm/test/CodeGen/PowerPC/anon_aggr.ll
index 9b32a8f55f3..f4e788849ec 100644
--- a/llvm/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/llvm/test/CodeGen/PowerPC/anon_aggr.ll
@@ -60,34 +60,33 @@ equal:
 unequal:
   ret i8* %array2_ptr
 }
+
 ; CHECK-LABEL: func2:
-; CHECK: cmpld {{([0-9]+,)?}}4, 6
-; CHECK-DAG: std 6, 72(1)
-; CHECK-DAG: std 5, 64(1)
-; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]]
+; CHECK: ld [[REG2:[0-9]+]], 72(1)
+; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]]
+; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
 ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET2]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
-; DARWIN32-LABEL: _func2
-; DARWIN32-DAG: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36
-; DARWIN32-DAG: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
+; DARWIN32: _func2:
+; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
+; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
 ; DARWIN32: mr
-; DARWIN32: mr r[[REG7:[0-9]+]], r5
-; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r5, r[[REG2]]
-; DARWIN32-DAG: stw r[[REG7]], -[[OFFSET1:[0-9]+]]
-; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
-; DARWIN32-DAG: lwz r3, -[[OFFSET1]]
-; DARWIN32-DAG: lwz r3, -[[OFFSET2]]
-
+; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
+; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
+; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
+; DARWIN32: lwz r3, -[[OFFSET1]]
+; DARWIN32: lwz r3, -[[OFFSET2]]
 
 ; DARWIN64: _func2:
 ; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
 ; DARWIN64: mr
 ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
 ; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
-; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
+; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
 ; DARWIN64: ld r3, -[[OFFSET1]]
 ; DARWIN64: ld r3, -[[OFFSET2]]
 
@@ -107,24 +106,24 @@ unequal:
 }
 
 ; CHECK-LABEL: func3:
-; CHECK: cmpld {{([0-9]+,)?}}4, 6
-; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]](1)
-; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]](1)
+; CHECK: ld [[REG3:[0-9]+]], 72(1)
+; CHECK: ld [[REG4:[0-9]+]], 56(1)
+; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]]
+; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)
+; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1)
 ; CHECK: ld 3, -[[OFFSET2]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
-; DARWIN32-LABEL: _func3:
-; DARWIN32-DAG: stw r[[REG8:[0-9]+]], 44(r[[REGSP:[0-9]+]])
-; DARWIN32-DAG: stw r[[REG5:[0-9]+]], 32(r[[REGSP]])
-; DARWIN32-DAG: addi r[[REG5a:[0-9]+]], r[[REGSP:[0-9]+]], 36
-; DARWIN32-DAG: addi r[[REG8a:[0-9]+]], r[[REGSP]], 24
-; DARWIN32-DAG: lwz r[[REG5a:[0-9]+]], 44(r[[REGSP]])
-; DARWIN32-DAG: lwz r[[REG8a:[0-9]+]], 32(r[[REGSP]])
-; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r[[REG8a]], r[[REG5a]]
-; DARWIN32-DAG: stw r[[REG5a]], -[[OFFSET1:[0-9]+]]
-; DARWIN32-DAG: stw r[[REG8a]], -[[OFFSET2:[0-9]+]]
-; DARWIN32-DAG: lwz r3, -[[OFFSET1:[0-9]+]]
-; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]]
+; DARWIN32: _func3:
+; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36
+; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24
+; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
+; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])
+; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
+; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
+; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]]
+; DARWIN32: lwz r3, -[[OFFSET2]]
+; DARWIN32: lwz r3, -[[OFFSET1]]
 
 ; DARWIN64: _func3:
 ; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
diff --git a/llvm/test/CodeGen/PowerPC/complex-return.ll b/llvm/test/CodeGen/PowerPC/complex-return.ll
index ec87a89b110..f6097e65512 100644
--- a/llvm/test/CodeGen/PowerPC/complex-return.ll
+++ b/llvm/test/CodeGen/PowerPC/complex-return.ll
@@ -24,10 +24,10 @@ entry:
 }
 
 ; CHECK-LABEL: foo:
-; CHECK-DAG: lfd 1
-; CHECK-DAG: lfd 2
-; CHECK-DAG: lfd 3
-; CHECK_DAG: lfd 4
+; CHECK: lfd 1
+; CHECK: lfd 2
+; CHECK: lfd 3
+; CHECK: lfd 4
 
 define { float, float } @oof() nounwind {
 entry:
@@ -50,6 +50,6 @@ entry:
 }
 
 ; CHECK-LABEL: oof:
-; CHECK-DAG: lfs 2
-; CHECK-DAG: lfs 1
+; CHECK: lfs 2
+; CHECK: lfs 1
 
diff --git a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
index 6128316f45f..b28b34d7814 100644
--- a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
+++ b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll
@@ -18,31 +18,31 @@ entry:
   ret void
 }
 
-; CHECK-DAG: std 3, 160(1)
-; CHECK-DAG: std 6, 184(1)
-; CHECK-DAG: std 5, 176(1)
-; CHECK-DAG: std 4, 168(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 167(1)
-; CHECK-DAG: lhz {{[0-9]+}}, 165(1)
-; CHECK-DAG: stb {{[0-9]+}}, 55(1)
-; CHECK-DAG-DAG: sth {{[0-9]+}}, 53(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 175(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 171(1)
-; CHECK-DAG: stb {{[0-9]+}}, 63(1)
-; CHECK-DAG: stw {{[0-9]+}}, 59(1)
-; CHECK-DAG: lhz {{[0-9]+}}, 182(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 178(1)
-; CHECK-DAG: sth {{[0-9]+}}, 70(1)
-; CHECK-DAG: stw {{[0-9]+}}, 66(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 191(1)
-; CHECK-DAG: lhz {{[0-9]+}}, 189(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 185(1)
-; CHECK-DAG: stb {{[0-9]+}}, 79(1)
-; CHECK-DAG: sth {{[0-9]+}}, 77(1)
-; CHECK-DAG: stw {{[0-9]+}}, 73(1)
-; CHECK-DAG: ld 6, 72(1)
-; CHECK-DAG: ld 5, 64(1)
-; CHECK-DAG: ld 4, 56(1)
-; CHECK-DAG: ld 3, 48(1)
+; CHECK: std 6, 184(1)
+; CHECK: std 5, 176(1)
+; CHECK: std 4, 168(1)
+; CHECK: std 3, 160(1)
+; CHECK: lbz {{[0-9]+}}, 167(1)
+; CHECK: lhz {{[0-9]+}}, 165(1)
+; CHECK: stb {{[0-9]+}}, 55(1)
+; CHECK: sth {{[0-9]+}}, 53(1)
+; CHECK: lbz {{[0-9]+}}, 175(1)
+; CHECK: lwz {{[0-9]+}}, 171(1)
+; CHECK: stb {{[0-9]+}}, 63(1)
+; CHECK: stw {{[0-9]+}}, 59(1)
+; CHECK: lhz {{[0-9]+}}, 182(1)
+; CHECK: lwz {{[0-9]+}}, 178(1)
+; CHECK: sth {{[0-9]+}}, 70(1)
+; CHECK: stw {{[0-9]+}}, 66(1)
+; CHECK: lbz {{[0-9]+}}, 191(1)
+; CHECK: lhz {{[0-9]+}}, 189(1)
+; CHECK: lwz {{[0-9]+}}, 185(1)
+; CHECK: stb {{[0-9]+}}, 79(1)
+; CHECK: sth {{[0-9]+}}, 77(1)
+; CHECK: stw {{[0-9]+}}, 73(1)
+; CHECK: ld 6, 72(1)
+; CHECK: ld 5, 64(1)
+; CHECK: ld 4, 56(1)
+; CHECK: ld 3, 48(1)
 
 declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
index d59dc64dcf8..c3cccd5b293 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck %s
 
 ; Verify internal alignment of long double in a struct.  The double
 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
@@ -19,44 +19,19 @@ entry:
   ret ppc_fp128 %0
 }
 
-; The additional stores are caused because we forward the value in the
-; store->load->bitcast path to make a store and bitcast of the same
-; value. Since the target does bitcast through memory and we no longer
-; remember the address we need to do the store in a fresh local
-; address. 
-
 ; CHECK-DAG: std 6, 72(1)
 ; CHECK-DAG: std 5, 64(1)
 ; CHECK-DAG: std 4, 56(1)
 ; CHECK-DAG: std 3, 48(1)
-
-; CHECK-DAG: std 5, -16(1)
-; CHECK-DAG: std 6, -8(1)
-; CHECK-DAG: lfd 1, -16(1)
-; CHECK-DAG: lfd 2, -8(1)
-
-; FIXMECHECK: lfd 1, 64(1)
-; FIXMECHECK: lfd 2, 72(1)
+; CHECK: lfd 1, 64(1)
+; CHECK: lfd 2, 72(1)
 
 ; CHECK-VSX-DAG: std 6, 72(1)
 ; CHECK-VSX-DAG: std 5, 64(1)
 ; CHECK-VSX-DAG: std 4, 56(1)
 ; CHECK-VSX-DAG: std 3, 48(1)
-; CHECK-VSX-DAG: std 5, -16(1)
-; CHECK-VSX-DAG: std 6, -8(1)
-; CHECK-VSX: addi 3, 1, -16
-; CHECK-VSX: lxsdx 1, 0, 3
-; CHECK-VSX: addi 3, 1, -8
-; CHECK-VSX: lxsdx 2, 0, 3
-
-; FIXME-VSX: addi 4, 1, 48
-; FIXME-VSX: lxsdx 1, 4, 3
-; FIXME-VSX: li 3, 24
-; FIXME-VSX: lxsdx 2, 4, 3
-
-; CHECK-P9: std 6, 72(1)
-; CHECK-P9: std 5, 64(1)
-; CHECK-P9: std 4, 56(1)
-; CHECK-P9: std 3, 48(1)
-; CHECK-P9: mtvsrd 1, 5
-; CHECK-P9: mtvsrd 2, 6
+; CHECK-VSX: li 3, 16
+; CHECK-VSX: addi 4, 1, 48
+; CHECK-VSX: lxsdx 1, 4, 3
+; CHECK-VSX: li 3, 24
+; CHECK-VSX: lxsdx 2, 4, 3
diff --git a/llvm/test/CodeGen/PowerPC/structsinmem.ll b/llvm/test/CodeGen/PowerPC/structsinmem.ll
index 01b0848e707..3777f3ec5ba 100644
--- a/llvm/test/CodeGen/PowerPC/structsinmem.ll
+++ b/llvm/test/CodeGen/PowerPC/structsinmem.ll
@@ -113,13 +113,13 @@ entry:
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
-; CHECK-DAG: lha {{[0-9]+}}, 126(1)
-; CHECK-DAG: lha {{[0-9]+}}, 132(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 119(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 140(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 144(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 152(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 160(1)
+; CHECK: lha {{[0-9]+}}, 126(1)
+; CHECK: lha {{[0-9]+}}, 132(1)
+; CHECK: lbz {{[0-9]+}}, 119(1)
+; CHECK: lwz {{[0-9]+}}, 140(1)
+; CHECK: lwz {{[0-9]+}}, 144(1)
+; CHECK: lwz {{[0-9]+}}, 152(1)
+; CHECK: lwz {{[0-9]+}}, 160(1)
 }
 
 define i32 @caller2() nounwind {
@@ -205,11 +205,11 @@ entry:
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
-; CHECK-DAG: lha {{[0-9]+}}, 126(1)
-; CHECK-DAG: lha {{[0-9]+}}, 133(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 119(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 140(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 147(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 154(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 161(1)
+; CHECK: lha {{[0-9]+}}, 126(1)
+; CHECK: lha {{[0-9]+}}, 133(1)
+; CHECK: lbz {{[0-9]+}}, 119(1)
+; CHECK: lwz {{[0-9]+}}, 140(1)
+; CHECK: lwz {{[0-9]+}}, 147(1)
+; CHECK: lwz {{[0-9]+}}, 154(1)
+; CHECK: lwz {{[0-9]+}}, 161(1)
 }
diff --git a/llvm/test/CodeGen/PowerPC/structsinregs.ll b/llvm/test/CodeGen/PowerPC/structsinregs.ll
index 54679f259e9..e27041dd4c8 100644
--- a/llvm/test/CodeGen/PowerPC/structsinregs.ll
+++ b/llvm/test/CodeGen/PowerPC/structsinregs.ll
@@ -59,7 +59,6 @@ entry:
   %call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7)
   ret i32 %call
 
-; CHECK-LABEL: caller1
 ; CHECK: ld 9, 112(31)
 ; CHECK: ld 8, 120(31)
 ; CHECK: ld 7, 128(31)
@@ -98,21 +97,20 @@ entry:
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
-; CHECK-LABEL: callee1
-; CHECK-DAG: std 9, 96(1)
-; CHECK-DAG: std 8, 88(1)
-; CHECK-DAG: std 7, 80(1)
-; CHECK-DAG: stw 6, 76(1)
-; CHECK-DAG: stw 5, 68(1)
-; CHECK-DAG: sth 4, 62(1)
-; CHECK-DAG: stb 3, 55(1)
-; CHECK-DAG: lha {{[0-9]+}}, 62(1)
-; CHECK-DAG: lha {{[0-9]+}}, 68(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 55(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 76(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 80(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 88(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 96(1)
+; CHECK: std 9, 96(1)
+; CHECK: std 8, 88(1)
+; CHECK: std 7, 80(1)
+; CHECK: stw 6, 76(1)
+; CHECK: stw 5, 68(1)
+; CHECK: sth 4, 62(1)
+; CHECK: stb 3, 55(1)
+; CHECK: lha {{[0-9]+}}, 62(1)
+; CHECK: lha {{[0-9]+}}, 68(1)
+; CHECK: lbz {{[0-9]+}}, 55(1)
+; CHECK: lwz {{[0-9]+}}, 76(1)
+; CHECK: lwz {{[0-9]+}}, 80(1)
+; CHECK: lwz {{[0-9]+}}, 88(1)
+; CHECK: lwz {{[0-9]+}}, 96(1)
 }
 
 define i32 @caller2() nounwind {
@@ -141,7 +139,6 @@ entry:
   %call = call i32 @callee2(%struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7)
   ret i32 %call
 
-; CHECK-LABEL: caller2
 ; CHECK: stb {{[0-9]+}}, 71(1)
 ; CHECK: sth {{[0-9]+}}, 69(1)
 ; CHECK: stb {{[0-9]+}}, 87(1)
@@ -187,19 +184,18 @@ entry:
   %add13 = add nsw i32 %add11, %6
   ret i32 %add13
 
-; CHECK-LABEL: callee2
-; CHECK-DAG: std 9, 96(1)
-; CHECK-DAG: std 8, 88(1)
-; CHECK-DAG: std 7, 80(1)
-; CHECK-DAG: stw 6, 76(1)
-; CHECK-DAG: std 5, 64(1)
-; CHECK-DAG: sth 4, 62(1)
-; CHECK-DAG: stb 3, 55(1)
-; CHECK-DAG: lha {{[0-9]+}}, 62(1)
-; CHECK-DAG: lha {{[0-9]+}}, 69(1)
-; CHECK-DAG: lbz {{[0-9]+}}, 55(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 76(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 83(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 90(1)
-; CHECK-DAG: lwz {{[0-9]+}}, 97(1)
+; CHECK: std 9, 96(1)
+; CHECK: std 8, 88(1)
+; CHECK: std 7, 80(1)
+; CHECK: stw 6, 76(1)
+; CHECK: std 5, 64(1)
+; CHECK: sth 4, 62(1)
+; CHECK: stb 3, 55(1)
+; CHECK: lha {{[0-9]+}}, 62(1)
+; CHECK: lha {{[0-9]+}}, 69(1)
+; CHECK: lbz {{[0-9]+}}, 55(1)
+; CHECK: lwz {{[0-9]+}}, 76(1)
+; CHECK: lwz {{[0-9]+}}, 83(1)
+; CHECK: lwz {{[0-9]+}}, 90(1)
+; CHECK: lwz {{[0-9]+}}, 97(1)
 }