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| author | Zaara Syeda <syzaara@ca.ibm.com> | 2016-11-15 17:54:19 +0000 |
|---|---|---|
| committer | Zaara Syeda <syzaara@ca.ibm.com> | 2016-11-15 17:54:19 +0000 |
| commit | a19c9e60e9aa50286ba340aa13bba8f541b25703 (patch) | |
| tree | cff75ce9dec78fa4c1dae44fa02d051e116fb934 /llvm/test/CodeGen/PowerPC | |
| parent | baf7ee3c5e405c13ed6d1e6aec5a8154764d9add (diff) | |
| download | bcm5719-llvm-a19c9e60e9aa50286ba340aa13bba8f541b25703.tar.gz bcm5719-llvm-a19c9e60e9aa50286ba340aa13bba8f541b25703.zip | |
vector load store with length (left justified) llvm portion
llvm-svn: 286993
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-p9.ll | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vsx-p9.ll b/llvm/test/CodeGen/PowerPC/vsx-p9.ll index b2a496cbe60..b0c6e851353 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-p9.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-p9.ll @@ -342,4 +342,50 @@ entry: ; Function Attrs: nounwind readnone declare <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16>) +; Function Attrs: nounwind readnone +define <4 x i32> @testLXVL(i8* %a, i64 %b) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvl(i8* %a, i64 %b) + ret <4 x i32> %0 +; CHECK-LABEL: testLXVL +; CHECK: lxvl 34, 3, 4 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.lxvl(i8*, i64) + +define void @testSTXVL(<4 x i32> %a, i8* %b, i64 %c) { +entry: + tail call void @llvm.ppc.vsx.stxvl(<4 x i32> %a, i8* %b, i64 %c) + ret void +; CHECK-LABEL: testSTXVL +; CHECK: stxvl 34, 5, 6 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare void @llvm.ppc.vsx.stxvl(<4 x i32>, i8*, i64) + +; Function Attrs: nounwind readnone +define <4 x i32> @testLXVLL(i8* %a, i64 %b) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvll(i8* %a, i64 %b) + ret <4 x i32> %0 +; CHECK-LABEL: testLXVLL +; CHECK: lxvll 34, 3, 4 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.vsx.lxvll(i8*, i64) + +define void @testSTXVLL(<4 x i32> %a, i8* %b, i64 %c) { +entry: + tail call void @llvm.ppc.vsx.stxvll(<4 x i32> %a, i8* %b, i64 %c) + ret void +; CHECK-LABEL: testSTXVLL +; CHECK: stxvll 34, 5, 6 +; CHECK: blr +} +; Function Attrs: nounwind readnone +declare void @llvm.ppc.vsx.stxvll(<4 x i32>, i8*, i64) + declare void @sink(...) |
