[PowerPC] enable optimizeCompareInstr for branch with static branch hint

In optimizeCompareInstr, a compare instruction is eliminated by using a record form instruction if possible.
If the branch instruction that uses the result of the compare has a static branch hint, the optimization does not happen.
This patch makes this optimization happen regardless of the branch hint by splitting branch hint and branch condition before checking the predicate to identify the possible optimizations.

Differential Revision: https://reviews.llvm.org/D35801

llvm-svn: 309255

1 files changed, 24 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
index 2aeb0e1f71f..b2f17e6a33b 100644
--- a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -54,3 +54,27 @@ foo:
 bar:
   ret i32 0
 }
+
+; This test case confirms that a record-form instruction is
+; generated even if the branch has a static branch hint.
+
+; CHECK-LABEL: fn4
+define i64 @fn4(i64 %a, i64 %b) {
+; CHECK: ADD8o
+; CHECK-NOT: CMP
+; CHECK: BCC 71
+
+entry:
+  %add = add nsw i64 %b, %a
+  %cmp = icmp eq i64 %add, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @exit(i32 signext 0) #3
+  unreachable
+
+if.end:
+  ret i64 %add
+}
+
+declare void @exit(i32 signext)