[PowerPC] Add handling for ColdCC calling convention and a pass to mark

candidates with coldcc attribute.

This patch adds support for the coldcc calling convention for Power.
This changes the set of non-volatile registers. It includes a pass to stress
test the implementation by marking all static directly called functions with
the coldcc attribute through the option -enable-coldcc-stress-test. It also
includes an option, -ppc-enable-coldcc, to add the coldcc attribute to
functions which are cold at all call sites based on BlockFrequencyInfo when
the containing function does not call any non cold functions.

Differential Revision: https://reviews.llvm.org/D38413

llvm-svn: 322721

2 files changed, 88 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/coldcc.ll b/llvm/test/CodeGen/PowerPC/coldcc.ll
new file mode 100644
index 00000000000..056e944321f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/coldcc.ll
@@ -0,0 +1,46 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu  < %s | FileCheck %s -check-prefix=COLDCC
+
+define signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %cold) {
+entry:
+  %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"(i32 %a, i32 %b)
+  %mul = mul nsw i32 %0, %cold
+  %tobool = icmp eq i32 %cold, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %mul1 = mul nsw i32 %mul, %cold
+  %mul2 = mul nsw i32 %b, %a
+  %call = tail call coldcc signext i32 @callee(i32 signext %a, i32 signext %b)
+  %add = add i32 %mul2, %a
+  %add3 = add i32 %add, %mul
+  %add4 = add i32 %add3, %mul1
+  %add5 = add i32 %add4, %call
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %f.0 = phi i32 [ %add5, %if.then ], [ %0, %entry ]
+  ret i32 %f.0
+}
+
+define internal coldcc signext i32 @callee(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
+entry:
+; COLDCC: @callee
+; COLDCC: std 6, -8(1)
+; COLDCC: std 7, -16(1)
+; COLDCC: std 8, -24(1)
+; COLDCC: std 9, -32(1)
+; COLDCC: std 10, -40(1)
+; COLDCC: ld 9, -32(1)
+; COLDCC: ld 8, -24(1)
+; COLDCC: ld 7, -16(1)
+; COLDCC: ld 10, -40(1)
+; COLDCC: ld 6, -8(1)
+  %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
+  %mul = mul nsw i32 %a, 3
+  %1 = mul i32 %b, -5
+  %add = add i32 %1, %mul
+  %sub = add i32 %add, %0
+  ret i32 %sub
+}
+
+attributes #0 = { noinline }
diff --git a/llvm/test/CodeGen/PowerPC/coldcc2.ll b/llvm/test/CodeGen/PowerPC/coldcc2.ll
new file mode 100644
index 00000000000..315198fca85
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/coldcc2.ll
@@ -0,0 +1,42 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=COLDCC
+
+%struct.MyStruct = type { i32, i32, i32, i32 }
+
+@caller.s = internal unnamed_addr global %struct.MyStruct zeroinitializer, align 8
+
+define signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %cold) {
+entry:
+; COLDCC: bl callee
+; COLDCC: ld 4, 40(1)
+; COLDCC: ld 5, 32(1)
+  %call = tail call coldcc { i64, i64 } @callee(i32 signext %a, i32 signext %b)
+  %0 = extractvalue { i64, i64 } %call, 0
+  %1 = extractvalue { i64, i64 } %call, 1
+  store i64 %0, i64* bitcast (%struct.MyStruct* @caller.s to i64*), align 8
+  store i64 %1, i64* bitcast (i32* getelementptr inbounds (%struct.MyStruct, %struct.MyStruct* @caller.s, i64 0, i32 2) to i64*), align 8
+  %2 = lshr i64 %1, 32
+  %3 = trunc i64 %2 to i32
+  %sub = sub nsw i32 0, %3
+  ret i32 %sub
+}
+
+define internal coldcc { i64, i64 } @callee(i32 signext %a, i32 signext %b) {
+entry:
+; COLDCC: std {{[0-9]+}}, 0(3)
+; COLDCC: std {{[0-9]+}}, 8(3)
+  %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
+  %mul = mul nsw i32 %a, 3
+  %1 = mul i32 %b, -5
+  %add = add i32 %1, %mul
+  %sub = add i32 %add, %0
+  %mul5 = mul nsw i32 %b, %a
+  %add6 = add nsw i32 %sub, %mul5
+  %retval.sroa.0.0.insert.ext = zext i32 %0 to i64
+  %retval.sroa.3.8.insert.ext = zext i32 %sub to i64
+  %retval.sroa.3.12.insert.ext = zext i32 %add6 to i64
+  %retval.sroa.3.12.insert.shift = shl nuw i64 %retval.sroa.3.12.insert.ext, 32
+  %retval.sroa.3.12.insert.insert = or i64 %retval.sroa.3.12.insert.shift, %retval.sroa.3.8.insert.ext
+  %.fca.0.insert = insertvalue { i64, i64 } undef, i64 %retval.sroa.0.0.insert.ext, 0
+  %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.sroa.3.12.insert.insert, 1
+  ret { i64, i64 } %.fca.1.insert
+}