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| author | Reid Spencer <rspencer@reidspencer.com> | 2007-01-17 07:59:14 +0000 |
|---|---|---|
| committer | Reid Spencer <rspencer@reidspencer.com> | 2007-01-17 07:59:14 +0000 |
| commit | 83b3d8267225d585678d5d3af9bba5735f4b415d (patch) | |
| tree | 9d6c2ad7bfd568186e83a39e6f03e1c0bf415715 /llvm/test/CodeGen/PowerPC | |
| parent | 100602d7561ca5e245db6194bddae86357d203d4 (diff) | |
| download | bcm5719-llvm-83b3d8267225d585678d5d3af9bba5735f4b415d.tar.gz bcm5719-llvm-83b3d8267225d585678d5d3af9bba5735f4b415d.zip | |
Regression is gone, don't try to find it on clean target.
llvm-svn: 33296
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
104 files changed, 2848 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/.cvsignore b/llvm/test/CodeGen/PowerPC/.cvsignore new file mode 100644 index 00000000000..7f2443f2f31 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/.cvsignore @@ -0,0 +1,3 @@ +Output +*.log +*.sum diff --git a/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll b/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll new file mode 100644 index 00000000000..e2a00d1e6e0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll @@ -0,0 +1,6 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +void %main() { + %tr1 = shr uint 1, ubyte 0 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll b/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll new file mode 100644 index 00000000000..4603bdbbf09 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll @@ -0,0 +1,6 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +void %main() { + %tr4 = shl ulong 1, ubyte 0 ; <ulong> [#uses=0] + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll b/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll new file mode 100644 index 00000000000..8f54c78e7a9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll @@ -0,0 +1,7 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +void %main() { + %shamt = add ubyte 0, 1 ; <ubyte> [#uses=1] + %tr2 = shr long 1, ubyte %shamt ; <long> [#uses=0] + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll b/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll new file mode 100644 index 00000000000..839e88c51ef --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll @@ -0,0 +1,3 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep '.comm.*X,0' + +%X = linkonce global {} {} diff --git a/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll b/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll new file mode 100644 index 00000000000..5dc4b28655a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +int %main() { + %setle = setle long 1, 0 + %select = select bool true, bool %setle, bool true + ret int 0 +} + diff --git a/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll b/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll new file mode 100644 index 00000000000..a4121c522fa --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll @@ -0,0 +1,3 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +long %test() { ret long undef } diff --git a/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll b/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll new file mode 100644 index 00000000000..ef0137f4cd6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll @@ -0,0 +1,12 @@ +; this should not crash the ppc backend + +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +uint %test( int %j.0.0.i) { + %tmp.85.i = and int %j.0.0.i, 7 + %tmp.161278.i = cast int %tmp.85.i to uint + %tmp.5.i77.i = shr uint %tmp.161278.i, ubyte 3 + ret uint %tmp.5.i77.i +} + + diff --git a/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll b/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll new file mode 100644 index 00000000000..1e748b752c9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll @@ -0,0 +1,9 @@ +; This function should have exactly one call to fixdfdi, no more! + +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mattr=-64bit | grep 'bl .*fixdfdi' | wc -l | grep 1 + +double %test2(double %tmp.7705) { + %mem_tmp.2.0.in = cast double %tmp.7705 to long ; <long> [#uses=1] + %mem_tmp.2.0 = cast long %mem_tmp.2.0.in to double + ret double %mem_tmp.2.0 +} diff --git a/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll b/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll new file mode 100644 index 00000000000..edbdc4a09d0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll @@ -0,0 +1,9 @@ +; This was erroneously being turned into an rlwinm instruction. +; The sign bit does matter in this case. + +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep srawi +int %test(int %X) { + %Y = and int %X, -2 + %Z = shr int %Y, ubyte 11 + ret int %Z +} diff --git a/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll b/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll new file mode 100644 index 00000000000..4264e9e82fe --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll @@ -0,0 +1,17 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc +target endian = big +target pointersize = 32 +target triple = "powerpc-apple-darwin8.2.0" +implementation ; Functions: + +void %bar(int %G, int %E, int %F, int %A, int %B, int %C, int %D, sbyte* %fmt, ...) { + %ap = alloca sbyte* ; <sbyte**> [#uses=2] + call void %llvm.va_start( sbyte** %ap ) + %tmp.1 = load sbyte** %ap ; <sbyte*> [#uses=1] + %tmp.0 = call double %foo( sbyte* %tmp.1 ) ; <double> [#uses=0] + ret void +} + +declare void %llvm.va_start(sbyte**) + +declare double %foo(sbyte*) diff --git a/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll b/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll new file mode 100644 index 00000000000..fd7f27d0bdb --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll @@ -0,0 +1,13 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc && +; RUN: llvm-upgrade < %s | llvm-as | llc | not grep ', f1' + +target endian = big +target pointersize = 32 +target triple = "powerpc-apple-darwin8.2.0" + +; Dead argument should reserve an FP register. +double %bar(double %DEAD, double %X, double %Y) { + %tmp.2 = add double %X, %Y + ret double %tmp.2 +} + diff --git a/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll new file mode 100644 index 00000000000..77004593283 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll @@ -0,0 +1,17 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc + +void %iterative_hash_host_wide_int() { + %zero = alloca int ; <int*> [#uses=2] + %b = alloca uint ; <uint*> [#uses=1] + store int 0, int* %zero + %tmp = load int* %zero ; <int> [#uses=1] + %tmp5 = cast int %tmp to uint ; <uint> [#uses=1] + %tmp6.u = add uint %tmp5, 32 ; <uint> [#uses=1] + %tmp6 = cast uint %tmp6.u to int ; <int> [#uses=1] + %tmp7 = load long* null ; <long> [#uses=1] + %tmp6 = cast int %tmp6 to ubyte ; <ubyte> [#uses=1] + %tmp8 = shr long %tmp7, ubyte %tmp6 ; <long> [#uses=1] + %tmp8 = cast long %tmp8 to uint ; <uint> [#uses=1] + store uint %tmp8, uint* %b + unreachable +} diff --git a/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll b/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll new file mode 100644 index 00000000000..dcf599b1a3b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll @@ -0,0 +1,7 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +double %CalcSpeed(float %tmp127) { + %tmp145 = cast float %tmp127 to double ; <double> [#uses=1] + %tmp150 = call double asm "frsqrte $0,$1", "=f,f"( double %tmp145 ) ; <double> [#uses=0] + ret double %tmp150 +} diff --git a/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll new file mode 100644 index 00000000000..a6918aa79d4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | grep 'vspltish v.*, 10' + +void %test(<8 x short>* %P) { + %tmp = load <8 x short>* %P ; <<8 x short>> [#uses=1] + %tmp1 = add <8 x short> %tmp, < short 10, short 10, short 10, short 10, short 10, short 10, short 10, short 10 > ; <<8 x short>> [#uses=1] + store <8 x short> %tmp1, <8 x short>* %P + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll b/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll new file mode 100644 index 00000000000..59f7ed4662b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll @@ -0,0 +1,72 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 + +void %test(sbyte* %stack) { +entry: + %tmp9 = seteq int 0, 0 ; <bool> [#uses=1] + %tmp30 = seteq uint 0, 0 ; <bool> [#uses=1] + br bool %tmp30, label %cond_next54, label %cond_true31 + +cond_true860: ; preds = %bb855 + %tmp879 = tail call <4 x float> %llvm.ppc.altivec.vmaddfp( <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x float> zeroinitializer ) ; <<4 x float>> [#uses=1] + %tmp880 = cast <4 x float> %tmp879 to <4 x int> ; <<4 x int>> [#uses=2] + %tmp883 = shufflevector <4 x int> %tmp880, <4 x int> undef, <4 x uint> < uint 1, uint 1, uint 1, uint 1 > ; <<4 x int>> [#uses=1] + %tmp883 = cast <4 x int> %tmp883 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp885 = shufflevector <4 x int> %tmp880, <4 x int> undef, <4 x uint> < uint 2, uint 2, uint 2, uint 2 > ; <<4 x int>> [#uses=1] + %tmp885 = cast <4 x int> %tmp885 to <4 x float> ; <<4 x float>> [#uses=1] + br label %cond_next905 + +cond_true31: ; preds = %entry + ret void + +cond_next54: ; preds = %entry + br bool %tmp9, label %cond_false385, label %bb279 + +bb279: ; preds = %cond_next54 + ret void + +cond_false385: ; preds = %cond_next54 + %tmp388 = seteq uint 0, 0 ; <bool> [#uses=1] + br bool %tmp388, label %cond_next463, label %cond_true389 + +cond_true389: ; preds = %cond_false385 + ret void + +cond_next463: ; preds = %cond_false385 + %tmp1208107 = setgt sbyte* null, %stack ; <bool> [#uses=1] + br bool %tmp1208107, label %cond_true1209.preheader, label %bb1212 + +cond_true498: ; preds = %cond_true1209.preheader + ret void + +cond_true519: ; preds = %cond_true1209.preheader + %bothcond = or bool false, false ; <bool> [#uses=1] + br bool %bothcond, label %bb855, label %bb980 + +cond_false548: ; preds = %cond_true1209.preheader + ret void + +bb855: ; preds = %cond_true519 + %tmp859 = seteq int 0, 0 ; <bool> [#uses=1] + br bool %tmp859, label %cond_true860, label %cond_next905 + +cond_next905: ; preds = %bb855, %cond_true860 + %vfpw2.4 = phi <4 x float> [ %tmp885, %cond_true860 ], [ undef, %bb855 ] ; <<4 x float>> [#uses=0] + %vfpw1.4 = phi <4 x float> [ %tmp883, %cond_true860 ], [ undef, %bb855 ] ; <<4 x float>> [#uses=0] + %tmp930 = cast <4 x float> zeroinitializer to <4 x int> ; <<4 x int>> [#uses=0] + ret void + +bb980: ; preds = %cond_true519 + ret void + +cond_true1209.preheader: ; preds = %cond_next463 + %tmp496 = and uint 0, 12288 ; <uint> [#uses=1] + switch uint %tmp496, label %cond_false548 [ + uint 0, label %cond_true498 + uint 4096, label %cond_true519 + ] + +bb1212: ; preds = %cond_next463 + ret void +} + +declare <4 x float> %llvm.ppc.altivec.vmaddfp(<4 x float>, <4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll new file mode 100644 index 00000000000..6c34cd7861a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll @@ -0,0 +1,60 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + + %struct.attr_desc = type { sbyte*, %struct.attr_desc*, %struct.attr_value*, %struct.attr_value*, uint } + %struct.attr_value = type { %struct.rtx_def*, %struct.attr_value*, %struct.insn_ent*, int, int } + %struct.insn_def = type { %struct.insn_def*, %struct.rtx_def*, int, int, int, int, int } + %struct.insn_ent = type { %struct.insn_ent*, %struct.insn_def* } + %struct.rtx_def = type { ushort, ubyte, ubyte, %struct.u } + %struct.u = type { [1 x long] } + +implementation ; Functions: + +void %find_attr() { +entry: + %tmp26 = seteq %struct.attr_desc* null, null ; <bool> [#uses=1] + br bool %tmp26, label %bb30, label %cond_true27 + +cond_true27: ; preds = %entry + ret void + +bb30: ; preds = %entry + %tmp67 = seteq %struct.attr_desc* null, null ; <bool> [#uses=1] + br bool %tmp67, label %cond_next92, label %cond_true68 + +cond_true68: ; preds = %bb30 + ret void + +cond_next92: ; preds = %bb30 + %tmp173 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=2] + %tmp174 = load uint* %tmp173 ; <uint> [#uses=1] + %tmp177 = and uint %tmp174, 4294967287 ; <uint> [#uses=1] + store uint %tmp177, uint* %tmp173 + %tmp180 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=1] + %tmp181 = load uint* %tmp180 ; <uint> [#uses=1] + %tmp185 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=2] + %tmp186 = load uint* %tmp185 ; <uint> [#uses=1] + %tmp183187 = shl uint %tmp181, ubyte 1 ; <uint> [#uses=1] + %tmp188 = and uint %tmp183187, 16 ; <uint> [#uses=1] + %tmp190 = and uint %tmp186, 4294967279 ; <uint> [#uses=1] + %tmp191 = or uint %tmp190, %tmp188 ; <uint> [#uses=1] + store uint %tmp191, uint* %tmp185 + %tmp193 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=1] + %tmp194 = load uint* %tmp193 ; <uint> [#uses=1] + %tmp198 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=2] + %tmp199 = load uint* %tmp198 ; <uint> [#uses=1] + %tmp196200 = shl uint %tmp194, ubyte 2 ; <uint> [#uses=1] + %tmp201 = and uint %tmp196200, 64 ; <uint> [#uses=1] + %tmp203 = and uint %tmp199, 4294967231 ; <uint> [#uses=1] + %tmp204 = or uint %tmp203, %tmp201 ; <uint> [#uses=1] + store uint %tmp204, uint* %tmp198 + %tmp206 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=1] + %tmp207 = load uint* %tmp206 ; <uint> [#uses=1] + %tmp211 = getelementptr %struct.attr_desc* null, int 0, uint 4 ; <uint*> [#uses=2] + %tmp212 = load uint* %tmp211 ; <uint> [#uses=1] + %tmp209213 = shl uint %tmp207, ubyte 1 ; <uint> [#uses=1] + %tmp214 = and uint %tmp209213, 128 ; <uint> [#uses=1] + %tmp216 = and uint %tmp212, 4294967167 ; <uint> [#uses=1] + %tmp217 = or uint %tmp216, %tmp214 ; <uint> [#uses=1] + store uint %tmp217, uint* %tmp211 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll new file mode 100644 index 00000000000..10260725f04 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll @@ -0,0 +1,16 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=powerpc64-apple-darwin | grep extsw | wc -l | grep 2 + +%lens = external global ubyte* +%vals = external global int* + +int %test(int %i) { + %tmp = load ubyte** %lens + %tmp1 = getelementptr ubyte* %tmp, int %i + %tmp = load ubyte* %tmp1 + %tmp2 = cast ubyte %tmp to int + %tmp3 = load int** %vals + %tmp5 = sub int 1, %tmp2 + %tmp6 = getelementptr int* %tmp3, int %tmp5 + %tmp7 = load int* %tmp6 + ret int %tmp7 +} diff --git a/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll new file mode 100644 index 00000000000..d71ba5a3822 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll @@ -0,0 +1,10 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +void %img2buf(int %symbol_size_in_bytes, ushort* %ui16) { + %tmp93 = load ushort* null ; <ushort> [#uses=1] + %tmp99 = call ushort %llvm.bswap.i16( ushort %tmp93 ) ; <ushort> [#uses=1] + store ushort %tmp99, ushort* %ui16 + ret void +} + +declare ushort %llvm.bswap.i16(ushort) diff --git a/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll new file mode 100644 index 00000000000..ab9ef35a0f1 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-08-11-RetVector.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vsldoi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vor + +<4 x float> %func(<4 x float> %fp0, <4 x float> %fp1) { + %tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x uint> < uint 0, uint 1, uint 2, uint 7 > ; <<4 x float>> [#uses=1] + ret <4 x float> %tmp76 +} + diff --git a/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll new file mode 100644 index 00000000000..287a79d29a9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll @@ -0,0 +1,38 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc + + %struct..0anon = type { int } + %struct.rtx_def = type { ushort, ubyte, ubyte, [1 x %struct..0anon] } + +implementation ; Functions: + +fastcc void %immed_double_const(int %i0, int %i1) { +entry: + %tmp1 = load uint* null ; <uint> [#uses=1] + switch uint %tmp1, label %bb103 [ + uint 1, label %bb + uint 3, label %bb + ] + +bb: ; preds = %entry, %entry + %tmp14 = setgt int 0, 31 ; <bool> [#uses=1] + br bool %tmp14, label %cond_next77, label %cond_next17 + +cond_next17: ; preds = %bb + ret void + +cond_next77: ; preds = %bb + %tmp79.not = setne int %i1, 0 ; <bool> [#uses=1] + %tmp84 = setlt int %i0, 0 ; <bool> [#uses=2] + %bothcond1 = or bool %tmp79.not, %tmp84 ; <bool> [#uses=1] + br bool %bothcond1, label %bb88, label %bb99 + +bb88: ; preds = %cond_next77 + %bothcond2 = and bool false, %tmp84 ; <bool> [#uses=0] + ret void + +bb99: ; preds = %cond_next77 + ret void + +bb103: ; preds = %entry + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll new file mode 100644 index 00000000000..58d1f265f67 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-09-28-shift_64.ll @@ -0,0 +1,27 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 +target endian = big +target pointersize = 64 +target triple = "powerpc64-apple-darwin8" + +implementation ; Functions: + +void %glArrayElement_CompExec() { +entry: + %tmp3 = and ulong 0, 18446744073701163007 ; <ulong> [#uses=1] + br label %cond_true24 + +cond_false: ; preds = %cond_true24 + ret void + +cond_true24: ; preds = %cond_true24, %entry + %indvar.ph = phi uint [ 0, %entry ], [ %indvar.next, %cond_true24 ] ; <uint> [#uses=1] + %indvar = add uint 0, %indvar.ph ; <uint> [#uses=2] + %code.0 = cast uint %indvar to ubyte ; <ubyte> [#uses=1] + %tmp5 = add ubyte %code.0, 16 ; <ubyte> [#uses=1] + %tmp7 = shr ulong %tmp3, ubyte %tmp5 ; <ulong> [#uses=1] + %tmp7 = cast ulong %tmp7 to int ; <int> [#uses=1] + %tmp8 = and int %tmp7, 1 ; <int> [#uses=1] + %tmp8 = seteq int %tmp8, 0 ; <bool> [#uses=1] + %indvar.next = add uint %indvar, 1 ; <uint> [#uses=1] + br bool %tmp8, label %cond_false, label %cond_true24 +} diff --git a/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll b/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll new file mode 100644 index 00000000000..72ba9932aec --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll @@ -0,0 +1,25 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -combiner-alias-analysis | grep 'f5' + +target endian = big +target pointersize = 32 +target triple = "powerpc-apple-darwin8.2.0" + %struct.Point = type { double, double, double } + +implementation ; Functions: + +void %offset(%struct.Point* %pt, double %x, double %y, double %z) { +entry: + %tmp = getelementptr %struct.Point* %pt, int 0, uint 0 ; <double*> [#uses=2] + %tmp = load double* %tmp ; <double> [#uses=1] + %tmp2 = add double %tmp, %x ; <double> [#uses=1] + store double %tmp2, double* %tmp + %tmp6 = getelementptr %struct.Point* %pt, int 0, uint 1 ; <double*> [#uses=2] + %tmp7 = load double* %tmp6 ; <double> [#uses=1] + %tmp9 = add double %tmp7, %y ; <double> [#uses=1] + store double %tmp9, double* %tmp6 + %tmp13 = getelementptr %struct.Point* %pt, int 0, uint 2 ; <double*> [#uses=2] + %tmp14 = load double* %tmp13 ; <double> [#uses=1] + %tmp16 = add double %tmp14, %z ; <double> [#uses=1] + store double %tmp16, double* %tmp13 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll new file mode 100644 index 00000000000..162cbdb1d37 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll @@ -0,0 +1,19 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep IMPLICIT_DEF + +void %foo(long %X) { +entry: + %tmp1 = and long %X, 3 ; <long> [#uses=1] + %tmp = setgt long %tmp1, 2 ; <bool> [#uses=1] + br bool %tmp, label %UnifiedReturnBlock, label %cond_true + +cond_true: ; preds = %entry + %tmp = tail call int (...)* %bar( ) ; <int> [#uses=0] + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare int %bar(...) + diff --git a/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll new file mode 100644 index 00000000000..397ada76c63 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll @@ -0,0 +1,24 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep xor + +target endian = big +target pointersize = 32 +target triple = "powerpc-apple-darwin8.7.0" + +implementation ; Functions: + +void %foo(int %X) { +entry: + %tmp1 = and int %X, 3 ; <int> [#uses=1] + %tmp2 = xor int %tmp1, 1 + %tmp = seteq int %tmp2, 0 ; <bool> [#uses=1] + br bool %tmp, label %UnifiedReturnBlock, label %cond_true + +cond_true: ; preds = %entry + tail call int (...)* %bar( ) ; <int> [#uses=0] + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare int %bar(...) diff --git a/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll b/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll new file mode 100644 index 00000000000..c981c269dc3 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll @@ -0,0 +1,6 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 + +int * %foo(uint %n) { + %A = alloca int, uint %n + ret int* %A +} diff --git a/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll b/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll new file mode 100644 index 00000000000..0411eb59306 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll @@ -0,0 +1,10 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 + +void %glgRunProcessor15() { + %tmp26355.i = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000 >, <4 x uint> < uint 0, uint 1, uint 2, uint 7 > ; <<4 x float>> [#uses=1] + %tmp3030030304.i = cast <4 x float> %tmp26355.i to <8 x short> ; <<8 x short>> [#uses=1] + %tmp30305.i = shufflevector <8 x short> zeroinitializer, <8 x short> %tmp3030030304.i, <8 x uint> < uint 1, uint 3, uint 5, uint 7, uint 9, uint 11, uint 13, uint 15 > ; <<8 x short>> [#uses=1] + %tmp30305.i = cast <8 x short> %tmp30305.i to <4 x int> ; <<4 x int>> [#uses=1] + store <4 x int> %tmp30305.i, <4 x int>* null + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll new file mode 100644 index 00000000000..8816ca003c9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll @@ -0,0 +1,26 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc + +void %bitap() { +entry: + %RMask.i = alloca [256 x uint], align 16 ; <[256 x uint]*> [#uses=1] + %buffer = alloca [147456 x sbyte], align 16 ; <[147456 x sbyte]*> [#uses=0] + br bool false, label %bb19, label %bb.preheader + +bb.preheader: ; preds = %entry + ret void + +bb19: ; preds = %entry + br bool false, label %bb12.i, label %cond_next39 + +bb12.i: ; preds = %bb12.i, %bb19 + %i.0.i = phi uint [ %tmp11.i, %bb12.i ], [ 0, %bb19 ] ; <uint> [#uses=2] + %tmp9.i = getelementptr [256 x uint]* %RMask.i, int 0, uint %i.0.i ; <uint*> [#uses=1] + store uint 0, uint* %tmp9.i + %tmp11.i = add uint %i.0.i, 1 ; <uint> [#uses=1] + br label %bb12.i + +cond_next39: ; preds = %bb19 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll new file mode 100644 index 00000000000..8c81db19a9e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll @@ -0,0 +1,27 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc + +%qsz.b = external global bool ; <bool*> [#uses=1] + +implementation ; Functions: + +fastcc void %qst() { +entry: + br bool true, label %cond_next71, label %cond_true + +cond_true: ; preds = %entry + ret void + +cond_next71: ; preds = %entry + %tmp73.b = load bool* %qsz.b ; <bool> [#uses=1] + %ii.4.ph = select bool %tmp73.b, ulong 4, ulong 0 ; <ulong> [#uses=1] + br label %bb139 + +bb82: ; preds = %bb139 + ret void + +bb139: ; preds = %bb139, %cond_next71 + %exitcond89 = seteq ulong 0, %ii.4.ph ; <bool> [#uses=1] + br bool %exitcond89, label %bb82, label %bb139 +} diff --git a/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll b/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll new file mode 100644 index 00000000000..06875f3ec92 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep extsb && +; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh + +define i32 %p1(i8 %c, i16 %s) { +entry: + %tmp = sext i8 %c to i32 ; <i32> [#uses=1] + %tmp1 = sext i16 %s to i32 ; <i32> [#uses=1] + %tmp2 = add i32 %tmp1, %tmp ; <i32> [#uses=1] + ret i32 %tmp2 +} diff --git a/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll new file mode 100644 index 00000000000..eecbb8176c4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep cntlzw + +define i32 %foo() { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %tmp = alloca i32, align 4 ; <i32*> [#uses=2] + %ctz_x = alloca i32, align 4 ; <i32*> [#uses=3] + %ctz_c = alloca i32, align 4 ; <i32*> [#uses=2] + "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 61440, i32* %ctz_x + %tmp = load i32* %ctz_x ; <i32> [#uses=1] + %tmp1 = sub i32 0, %tmp ; <i32> [#uses=1] + %tmp2 = load i32* %ctz_x ; <i32> [#uses=1] + %tmp3 = and i32 %tmp1, %tmp2 ; <i32> [#uses=1] + %tmp4 = call i32 asm "$(cntlz$|cntlzw$) $0,$1", "=r,r,~{dirflag},~{fpsr},~{flags}"( i32 %tmp3 ) ; <i32> [#uses=1] + store i32 %tmp4, i32* %ctz_c + %tmp5 = load i32* %ctz_c ; <i32> [#uses=1] + store i32 %tmp5, i32* %tmp + %tmp6 = load i32* %tmp ; <i32> [#uses=1] + store i32 %tmp6, i32* %retval + br label %return + +return: ; preds = %entry + %retval = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval +} diff --git a/llvm/test/CodeGen/PowerPC/Frames-align.ll b/llvm/test/CodeGen/PowerPC/Frames-align.ll new file mode 100644 index 00000000000..6ff5eeb77de --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/Frames-align.ll @@ -0,0 +1,11 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'rlwinm r0, r1, 0, 22, 31' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'subfic r0, r0, -17408' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'rldicl r0, r1, 0, 54' + + +implementation + +int* %f1() { + %tmp = alloca int, uint 4095, align 1024 + ret int* %tmp +} diff --git a/llvm/test/CodeGen/PowerPC/Frames-alloca.ll b/llvm/test/CodeGen/PowerPC/Frames-alloca.ll new file mode 100644 index 00000000000..895d8369b60 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/Frames-alloca.ll @@ -0,0 +1,24 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'stwu r1, -64(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'lwz r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stwu r1, -64(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lwz r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'stdu r1, -112(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'ld r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'ld r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stdu r1, -112(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ld r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ld r31, 40(r1)' + + +implementation + +int* %f1(uint %n) { + %tmp = alloca int, uint %n + ret int* %tmp +} diff --git a/llvm/test/CodeGen/PowerPC/Frames-large.ll b/llvm/test/CodeGen/PowerPC/Frames-large.ll new file mode 100644 index 00000000000..36532266860 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/Frames-large.ll @@ -0,0 +1,32 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | not grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'lis r0, -1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'ori r0, r0, 32704' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'stwux r1, r1, r0' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'lwz r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | not grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lis r0, -1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ori r0, r0, 32704' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stwux r1, r1, r0' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lwz r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | not grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'lis r0, -1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'ori r0, r0, 32656' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'stdux r1, r1, r0' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'ld r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | not grep 'ld r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lis r0, -1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ori r0, r0, 32656' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stdux r1, r1, r0' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ld r1, 0(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ld r31, 40(r1)' + + +implementation + +int* %f1() { + %tmp = alloca int, uint 8191 + ret int* %tmp +} diff --git a/llvm/test/CodeGen/PowerPC/Frames-leaf.ll b/llvm/test/CodeGen/PowerPC/Frames-leaf.ll new file mode 100644 index 00000000000..933ca121adc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/Frames-leaf.ll @@ -0,0 +1,24 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep 'stwu r1, -.*(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep 'addi r1, r1, ' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -disable-fp-elim | not grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -disable-fp-elim | not grep 'stwu r1, -.*(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -disable-fp-elim | not grep 'addi r1, r1, ' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -disable-fp-elim | not grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | not grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | not grep 'stdu r1, -.*(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | not grep 'addi r1, r1, ' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | not grep 'ld r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -disable-fp-elim | not grep 'stw r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -disable-fp-elim | not grep 'stdu r1, -.*(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -disable-fp-elim | not grep 'addi r1, r1, ' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -disable-fp-elim | not grep 'ld r31, 40(r1)' + + +implementation + +int* %f1() { + %tmp = alloca int, uint 2 + ret int* %tmp +} diff --git a/llvm/test/CodeGen/PowerPC/Frames-small.ll b/llvm/test/CodeGen/PowerPC/Frames-small.ll new file mode 100644 index 00000000000..e40b11cddb3 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/Frames-small.ll @@ -0,0 +1,24 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | not grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'stwu r1, -16448(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'addi r1, r1, 16448' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | not grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stw r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stwu r1, -16448(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'addi r1, r1, 16448' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'lwz r31, 20(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | not grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'stdu r1, -16496(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | grep 'addi r1, r1, 16496' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | not grep 'ld r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'std r31, 40(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'stdu r1, -16496(r1)' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'addi r1, r1, 16496' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | grep 'ld r31, 40(r1)' + + +implementation + +int* %f1() { + %tmp = alloca int, uint 4095 + ret int* %tmp +} diff --git a/llvm/test/CodeGen/PowerPC/addc.ll b/llvm/test/CodeGen/PowerPC/addc.ll new file mode 100644 index 00000000000..25f38547cc2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/addc.ll @@ -0,0 +1,26 @@ +; All of these should be codegen'd without loading immediates +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep addc | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep adde | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep addze | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep addme | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep addic | wc -l | grep 2 + +implementation ; Functions: + +long %add_ll(long %a, long %b) { +entry: + %tmp.2 = add long %b, %a ; <long> [#uses=1] + ret long %tmp.2 +} + +long %add_l_5(long %a) { +entry: + %tmp.1 = add long %a, 5 ; <long> [#uses=1] + ret long %tmp.1 +} + +long %add_l_m5(long %a) { +entry: + %tmp.1 = add long %a, -5 ; <long> [#uses=1] + ret long %tmp.1 +} diff --git a/llvm/test/CodeGen/PowerPC/addi-reassoc.ll b/llvm/test/CodeGen/PowerPC/addi-reassoc.ll new file mode 100644 index 00000000000..7cfbd8653f5 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/addi-reassoc.ll @@ -0,0 +1,21 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep addi + + %struct.X = type { [5 x sbyte] } +implementation ; Functions: + +int %test1([4 x int]* %P, int %i) { + %tmp.2 = add int %i, 2 ; <int> [#uses=1] + %tmp.4 = getelementptr [4 x int]* %P, int %tmp.2, int 1 + %tmp.5 = load int* %tmp.4 + ret int %tmp.5 +} + +int %test2(%struct.X* %P, int %i) { + %tmp.2 = add int %i, 2 + %tmp.5 = getelementptr %struct.X* %P, int %tmp.2, uint 0, int 1 + %tmp.6 = load sbyte* %tmp.5 + %tmp.7 = cast sbyte %tmp.6 to int + ret int %tmp.7 +} + diff --git a/llvm/test/CodeGen/PowerPC/align.ll b/llvm/test/CodeGen/PowerPC/align.ll new file mode 100644 index 00000000000..e74b6091686 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/align.ll @@ -0,0 +1,9 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep "align.4" | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep "align.2" | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep "align.3" | wc -l | grep 1 + + +%A = global <4 x uint> < uint 10, uint 20, uint 30, uint 40 > +%B = global float 1.000000e+02 +%C = global double 2.000000e+03 + diff --git a/llvm/test/CodeGen/PowerPC/and-branch.ll b/llvm/test/CodeGen/PowerPC/and-branch.ll new file mode 100644 index 00000000000..ef53d6c314e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/and-branch.ll @@ -0,0 +1,19 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep mfcr + +void %foo(int %X, int %Y, int %Z) { +entry: + %tmp = seteq int %X, 0 ; <bool> [#uses=1] + %tmp3 = setlt int %Y, 5 ; <bool> [#uses=1] + %tmp4 = and bool %tmp3, %tmp ; <bool> [#uses=1] + br bool %tmp4, label %cond_true, label %UnifiedReturnBlock + +cond_true: ; preds = %entry + %tmp5 = tail call int (...)* %bar( ) ; <int> [#uses=0] + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare int %bar(...) diff --git a/llvm/test/CodeGen/PowerPC/and-elim.ll b/llvm/test/CodeGen/PowerPC/and-elim.ll new file mode 100644 index 00000000000..8f423d8be1e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/and-elim.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=ppc32 && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwin + +define void %test(i8* %P) { + %W = load i8* %P + %X = shl i8 %W, i8 1 + %Y = add i8 %X, 2 + %Z = and i8 %Y, 254 ; dead and + store i8 %Z, i8* %P + ret void +} + +define i16 %test2(i16 zext %crc) zext { + ; No and's should be needed for the i16s here. + %tmp.1 = lshr i16 %crc, i8 1 + %tmp.7 = xor i16 %tmp.1, 40961 + ret i16 %tmp.7 +} + diff --git a/llvm/test/CodeGen/PowerPC/and-imm.ll b/llvm/test/CodeGen/PowerPC/and-imm.ll new file mode 100644 index 00000000000..e81f7768a60 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/and-imm.ll @@ -0,0 +1,12 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep 'ori\|lis' + +int %test(int %X) { + %Y = and int %X, 32769 ; andi. r3, r3, 32769 + ret int %Y +} + +int %test2(int %X) { + %Y = and int %X, -2147418112 ; andis. r3, r3, 32769 + ret int %Y +} + diff --git a/llvm/test/CodeGen/PowerPC/and_add.ll b/llvm/test/CodeGen/PowerPC/and_add.ll new file mode 100644 index 00000000000..dc82fc94402 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/and_add.ll @@ -0,0 +1,11 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep slwi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep addi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep rlwinm + +int %test(int %A) { + %B = mul int %A, 8 ;; shift + %C = add int %B, 7 ;; dead, no demanded bits. + %D = and int %C, -8 ;; dead once add is gone. + ret int %D +} + diff --git a/llvm/test/CodeGen/PowerPC/and_sext.ll b/llvm/test/CodeGen/PowerPC/and_sext.ll new file mode 100644 index 00000000000..f025e21e5d7 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/and_sext.ll @@ -0,0 +1,29 @@ +; These tests should not contain a sign extend. +; RUN: llvm-as < %s | llc -march=ppc32 && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb + +define i32 %test1(i32 %mode.0.i.0) { + %tmp.79 = trunc i32 %mode.0.i.0 to i16 + %tmp.80 = sext i16 %tmp.79 to i32 + %tmp.81 = and i32 %tmp.80, 24 + ret i32 %tmp.81 +} + +define i16 %test2(i16 sext %X, i16 sext %x) sext { + %tmp = sext i16 %X to i32 + %tmp1 = sext i16 %x to i32 + %tmp2 = add i32 %tmp, %tmp1 + %tmp4 = ashr i32 %tmp2, i8 1 + %tmp4 = trunc i32 %tmp4 to i16 + %tmp45 = sext i16 %tmp4 to i32 + %retval = trunc i32 %tmp45 to i16 + ret i16 %retval +} + +define i16 %test3(i32 zext %X) sext { + %tmp1 = lshr i32 %X, i8 16 + %tmp1 = trunc i32 %tmp1 to i16 + ret i16 %tmp1 +} + diff --git a/llvm/test/CodeGen/PowerPC/and_sra.ll b/llvm/test/CodeGen/PowerPC/and_sra.ll new file mode 100644 index 00000000000..abfa9f113ad --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/and_sra.ll @@ -0,0 +1,26 @@ +; Neither of these functions should contain algebraic right shifts +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srawi + +int %test1(uint %mode.0.i.0) { + %tmp.79 = cast uint %mode.0.i.0 to int ; <sbyte> [#uses=1] + %tmp.80 = shr int %tmp.79, ubyte 15 ; <int> [#uses=1] + %tmp.81 = and int %tmp.80, 24 ; <int> [#uses=1] + ret int %tmp.81 +} + +int %test2(uint %mode.0.i.0) { + %tmp.79 = cast uint %mode.0.i.0 to int ; <sbyte> [#uses=1] + %tmp.80 = shr int %tmp.79, ubyte 15 ; <int> [#uses=1] + %tmp.81 = shr uint %mode.0.i.0, ubyte 16 + %tmp.82 = cast uint %tmp.81 to int + %tmp.83 = and int %tmp.80, %tmp.82 ; <int> [#uses=1] + ret int %tmp.83 +} + +uint %test3(int %specbits.6.1) { + %tmp.2540 = shr int %specbits.6.1, ubyte 11 ; <int> [#uses=1] + %tmp.2541 = cast int %tmp.2540 to uint ; <uint> [#uses=1] + %tmp.2542 = shl uint %tmp.2541, ubyte 13 ; <uint> [#uses=1] + %tmp.2543 = and uint %tmp.2542, 8192 ; <uint> [#uses=1] + ret uint %tmp.2543 +} diff --git a/llvm/test/CodeGen/PowerPC/branch-opt.ll b/llvm/test/CodeGen/PowerPC/branch-opt.ll new file mode 100644 index 00000000000..7f40a2d8668 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/branch-opt.ll @@ -0,0 +1,93 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'b LBB.*cond_next48.loopexit' | wc -l | grep 1 + +target endian = big +target pointersize = 32 +target triple = "powerpc-apple-darwin8.7.0" + +implementation ; Functions: + +void %foo(int %W, int %X, int %Y, int %Z) { +entry: + %X = cast int %X to uint ; <uint> [#uses=1] + %Y = cast int %Y to uint ; <uint> [#uses=1] + %Z = cast int %Z to uint ; <uint> [#uses=1] + %W = cast int %W to uint ; <uint> [#uses=1] + %tmp1 = and int %W, 1 ; <int> [#uses=1] + %tmp1 = seteq int %tmp1, 0 ; <bool> [#uses=1] + br bool %tmp1, label %cond_false, label %bb5 + +bb: ; preds = %bb5, %bb + %indvar77 = phi uint [ %indvar.next78, %bb ], [ 0, %bb5 ] ; <uint> [#uses=1] + %tmp2 = tail call int (...)* %bar( ) ; <int> [#uses=0] + %indvar.next78 = add uint %indvar77, 1 ; <uint> [#uses=2] + %exitcond79 = seteq uint %indvar.next78, %X ; <bool> [#uses=1] + br bool %exitcond79, label %cond_next48, label %bb + +bb5: ; preds = %entry + %tmp = seteq int %X, 0 ; <bool> [#uses=1] + br bool %tmp, label %cond_next48, label %bb + +cond_false: ; preds = %entry + %tmp10 = and int %W, 2 ; <int> [#uses=1] + %tmp10 = seteq int %tmp10, 0 ; <bool> [#uses=1] + br bool %tmp10, label %cond_false20, label %bb16 + +bb12: ; preds = %bb16, %bb12 + %indvar72 = phi uint [ %indvar.next73, %bb12 ], [ 0, %bb16 ] ; <uint> [#uses=1] + %tmp13 = tail call int (...)* %bar( ) ; <int> [#uses=0] + %indvar.next73 = add uint %indvar72, 1 ; <uint> [#uses=2] + %exitcond74 = seteq uint %indvar.next73, %Y ; <bool> [#uses=1] + br bool %exitcond74, label %cond_next48, label %bb12 + +bb16: ; preds = %cond_false + %tmp18 = seteq int %Y, 0 ; <bool> [#uses=1] + br bool %tmp18, label %cond_next48, label %bb12 + +cond_false20: ; preds = %cond_false + %tmp23 = and int %W, 4 ; <int> [#uses=1] + %tmp23 = seteq int %tmp23, 0 ; <bool> [#uses=1] + br bool %tmp23, label %cond_false33, label %bb29 + +bb25: ; preds = %bb29, %bb25 + %indvar67 = phi uint [ %indvar.next68, %bb25 ], [ 0, %bb29 ] ; <uint> [#uses=1] + %tmp26 = tail call int (...)* %bar( ) ; <int> [#uses=0] + %indvar.next68 = add uint %indvar67, 1 ; <uint> [#uses=2] + %exitcond69 = seteq uint %indvar.next68, %Z ; <bool> [#uses=1] + br bool %exitcond69, label %cond_next48, label %bb25 + +bb29: ; preds = %cond_false20 + %tmp31 = seteq int %Z, 0 ; <bool> [#uses=1] + br bool %tmp31, label %cond_next48, label %bb25 + +cond_false33: ; preds = %cond_false20 + %tmp36 = and int %W, 8 ; <int> [#uses=1] + %tmp36 = seteq int %tmp36, 0 ; <bool> [#uses=1] + br bool %tmp36, label %cond_next48, label %bb42 + +bb38: ; preds = %bb42 + %tmp39 = tail call int (...)* %bar( ) ; <int> [#uses=0] + %indvar.next = add uint %indvar, 1 ; <uint> [#uses=1] + br label %bb42 + +bb42: ; preds = %cond_false33, %bb38 + %indvar = phi uint [ %indvar.next, %bb38 ], [ 0, %cond_false33 ] ; <uint> [#uses=3] + %indvar = cast uint %indvar to int ; <int> [#uses=1] + %W_addr.0 = sub int %W, %indvar ; <int> [#uses=1] + %exitcond = seteq uint %indvar, %W ; <bool> [#uses=1] + br bool %exitcond, label %cond_next48, label %bb38 + +cond_next48: ; preds = %bb, %bb12, %bb25, %bb42, %cond_false33, %bb29, %bb16, %bb5 + %W_addr.1 = phi int [ %W, %bb5 ], [ %W, %bb16 ], [ %W, %bb29 ], [ %W, %cond_false33 ], [ %W_addr.0, %bb42 ], [ %W, %bb25 ], [ %W, %bb12 ], [ %W, %bb ] ; <int> [#uses=1] + %tmp50 = seteq int %W_addr.1, 0 ; <bool> [#uses=1] + br bool %tmp50, label %UnifiedReturnBlock, label %cond_true51 + +cond_true51: ; preds = %cond_next48 + %tmp52 = tail call int (...)* %bar( ) ; <int> [#uses=0] + ret void + +UnifiedReturnBlock: ; preds = %cond_next48 + ret void +} + +declare int %bar(...) diff --git a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll new file mode 100644 index 00000000000..853abc42558 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll @@ -0,0 +1,42 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'stwbrx\|lwbrx\|sthbrx\|lhbrx' | wc -l | grep 4 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep rlwinm && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep rlwimi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | grep 'stwbrx\|lwbrx\|sthbrx\|lhbrx' | wc -l | grep 4 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | not grep rlwinm && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 | not grep rlwimi + +void %STWBRX(uint %i, sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to uint* + %tmp13 = tail call uint %llvm.bswap.i32(uint %i) + store uint %tmp13, uint* %tmp1 + ret void +} + +uint %LWBRX(sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to uint* + %tmp = load uint* %tmp1 + %tmp14 = tail call uint %llvm.bswap.i32( uint %tmp ) + ret uint %tmp14 +} + +void %STHBRX(ushort %s, sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to ushort* + %tmp5 = call ushort %llvm.bswap.i16( ushort %s ) + store ushort %tmp5, ushort* %tmp1 + ret void +} + +ushort %LHBRX(sbyte* %ptr, int %off) { + %tmp1 = getelementptr sbyte* %ptr, int %off + %tmp1 = cast sbyte* %tmp1 to ushort* + %tmp = load ushort* %tmp1 + %tmp6 = call ushort %llvm.bswap.i16(ushort %tmp) + ret ushort %tmp6 +} + +declare uint %llvm.bswap.i32(uint) + +declare ushort %llvm.bswap.i16(ushort) diff --git a/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll new file mode 100644 index 00000000000..6e41a59ceef --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll @@ -0,0 +1,23 @@ +; There should be exactly one vxor here. +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vxor | wc -l | grep 1 && + +; There should be exactly one vsplti here. +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vsplti | wc -l | grep 1 + + +void %VXOR(<4 x float>* %P1, <4 x int>* %P2, <4 x float>* %P3) { + %tmp = load <4 x float>* %P3 + %tmp3 = load <4 x float>* %P1 + %tmp4 = mul <4 x float> %tmp, %tmp3 + store <4 x float> %tmp4, <4 x float>* %P3 + store <4 x float> zeroinitializer, <4 x float>* %P1 + store <4 x int> zeroinitializer, <4 x int>* %P2 + ret void +} + +void %VSPLTI(<4 x int>* %P2, <8 x short>* %P3) { + store <4 x int> cast (<16 x sbyte> < sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1 > to <4 x int>), <4 x int>* %P2 + store <8 x short> < short -1, short -1, short -1, short -1, short -1, short -1, short -1, short -1 >, <8 x short>* %P3 + ret void +} + diff --git a/llvm/test/CodeGen/PowerPC/calls.ll b/llvm/test/CodeGen/PowerPC/calls.ll new file mode 100644 index 00000000000..73aa2aa2d4b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/calls.ll @@ -0,0 +1,28 @@ +; Test various forms of calls. + +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'bl ' | wc -l | grep 2 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'bctrl' | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'bla ' | wc -l | grep 1 + +declare void %foo() + +void %test_direct() { + call void %foo() + ret void +} + +void %test_extsym(sbyte *%P) { + free sbyte* %P + ret void +} + +void %test_indirect(void()* %fp) { + call void %fp() + ret void +} + +void %test_abs() { + %fp = cast int 400 to void()* + call void %fp() + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/cmp-cmp.ll b/llvm/test/CodeGen/PowerPC/cmp-cmp.ll new file mode 100644 index 00000000000..d505736005c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/cmp-cmp.ll @@ -0,0 +1,16 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep mfcr + +void %test(long %X) { + %tmp1 = and long %X, 3 ; <long> [#uses=1] + %tmp = setgt long %tmp1, 2 ; <bool> [#uses=1] + br bool %tmp, label %UnifiedReturnBlock, label %cond_true + +cond_true: ; preds = %entry + tail call void %test(long 0) + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + diff --git a/llvm/test/CodeGen/PowerPC/constants.ll b/llvm/test/CodeGen/PowerPC/constants.ll new file mode 100644 index 00000000000..37164cb4c94 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/constants.ll @@ -0,0 +1,51 @@ +; All of these routines should be perform optimal load of constants. +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep lis | wc -l | grep 5 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep ori | wc -l | grep 3 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep 'li ' | wc -l | grep 4 + +implementation ; Functions: + +int %f1() { +entry: + ret int 1 +} + +int %f2() { +entry: + ret int -1 +} + +int %f3() { +entry: + ret int 0 +} + +int %f4() { +entry: + ret int 32767 +} + +int %f5() { +entry: + ret int 65535 +} + +int %f6() { +entry: + ret int 65536 +} + +int %f7() { +entry: + ret int 131071 +} + +int %f8() { +entry: + ret int 2147483647 +} + +int %f9() { +entry: + ret int -2147483648 +} diff --git a/llvm/test/CodeGen/PowerPC/cttz.ll b/llvm/test/CodeGen/PowerPC/cttz.ll new file mode 100644 index 00000000000..28e711a1c77 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/cttz.ll @@ -0,0 +1,12 @@ +; Make sure this testcase does not use ctpop +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep -i 'cntlzw' + +declare uint %llvm.cttz.i32(uint) + +implementation ; Functions: + +uint %bar(uint %x) { +entry: + %tmp.1 = call uint %llvm.cttz.i32( uint %x ) + ret uint %tmp.1 +} diff --git a/llvm/test/CodeGen/PowerPC/darwin-labels.ll b/llvm/test/CodeGen/PowerPC/darwin-labels.ll new file mode 100644 index 00000000000..8178c8401c8 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/darwin-labels.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc | grep 'foo bar":' + +target endian = big +target pointersize = 32 +target triple = "powerpc-apple-darwin8.2.0" + +"foo bar" = global int 4 + diff --git a/llvm/test/CodeGen/PowerPC/dg.exp b/llvm/test/CodeGen/PowerPC/dg.exp new file mode 100644 index 00000000000..142de8a6c8f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/dg.exp @@ -0,0 +1,3 @@ +load_lib llvm-dg.exp + +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version diff --git a/llvm/test/CodeGen/PowerPC/div-2.ll b/llvm/test/CodeGen/PowerPC/div-2.ll new file mode 100644 index 00000000000..d89361820ab --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/div-2.ll @@ -0,0 +1,29 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srawi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep blr + +int %test1(int %X) { + %Y = and int %X, 15 + %Z = div int %Y, 4 + ret int %Z +} + +int %test2(int %W) { + %X = and int %W, 15 + %Y = sub int 16, %X + %Z = div int %Y, 4 + ret int %Z +} + +int %test3(int %W) { + %X = and int %W, 15 + %Y = sub int 15, %X + %Z = div int %Y, 4 + ret int %Z +} + +int %test4(int %W) { + %X = and int %W, 2 + %Y = sub int 5, %X + %Z = div int %Y, 2 + ret int %Z +} diff --git a/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll new file mode 100644 index 00000000000..a2ab4e1a81a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll @@ -0,0 +1,89 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep eqv | wc -l | grep 3 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep andc | wc -l | grep 3 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep orc | wc -l | grep 2 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep nor | wc -l | grep 3 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep nand | wc -l | grep 1 + +int %EQV1(int %X, int %Y) { + %A = xor int %X, %Y + %B = xor int %A, -1 + ret int %B +} + +int %EQV2(int %X, int %Y) { + %A = xor int %X, -1 + %B = xor int %A, %Y + ret int %B +} + +int %EQV3(int %X, int %Y) { + %A = xor int %X, -1 + %B = xor int %Y, %A + ret int %B +} + +int %ANDC1(int %X, int %Y) { + %A = xor int %Y, -1 + %B = and int %X, %A + ret int %B +} + +int %ANDC2(int %X, int %Y) { + %A = xor int %X, -1 + %B = and int %A, %Y + ret int %B +} + +int %ORC1(int %X, int %Y) { + %A = xor int %Y, -1 + %B = or int %X, %A + ret int %B +} + +int %ORC2(int %X, int %Y) { + %A = xor int %X, -1 + %B = or int %A, %Y + ret int %B +} + +int %NOR1(int %X) { + %Y = xor int %X, -1 + ret int %Y +} + +int %NOR2(int %X, int %Y) { + %Z = or int %X, %Y + %R = xor int %Z, -1 + ret int %R +} + +int %NAND1(int %X, int %Y) { + %Z = and int %X, %Y + %W = xor int %Z, -1 + ret int %W +} + +void %VNOR(<4 x float>* %P, <4 x float>* %Q) { + %tmp = load <4 x float>* %P + %tmp = cast <4 x float> %tmp to <4 x int> + %tmp2 = load <4 x float>* %Q + %tmp2 = cast <4 x float> %tmp2 to <4 x int> + %tmp3 = or <4 x int> %tmp, %tmp2 + %tmp4 = xor <4 x int> %tmp3, < int -1, int -1, int -1, int -1 > + %tmp4 = cast <4 x int> %tmp4 to <4 x float> + store <4 x float> %tmp4, <4 x float>* %P + ret void +} + +void %VANDC(<4 x float>* %P, <4 x float>* %Q) { + %tmp = load <4 x float>* %P + %tmp = cast <4 x float> %tmp to <4 x int> + %tmp2 = load <4 x float>* %Q + %tmp2 = cast <4 x float> %tmp2 to <4 x int> + %tmp4 = xor <4 x int> %tmp2, < int -1, int -1, int -1, int -1 > + %tmp3 = and <4 x int> %tmp, %tmp4 + %tmp4 = cast <4 x int> %tmp3 to <4 x float> + store <4 x float> %tmp4, <4 x float>* %P + ret void +} + diff --git a/llvm/test/CodeGen/PowerPC/extsh.ll b/llvm/test/CodeGen/PowerPC/extsh.ll new file mode 100644 index 00000000000..0f4f512a25e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/extsh.ll @@ -0,0 +1,7 @@ +; This should turn into a single extsh +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep extsh | wc -l | grep 1 +int %test(int %X) { + %tmp.81 = shl int %X, ubyte 16 ; <int> [#uses=1] + %tmp.82 = shr int %tmp.81, ubyte 16 ; <int> [#uses=1] + ret int %tmp.82 +} diff --git a/llvm/test/CodeGen/PowerPC/fma.ll b/llvm/test/CodeGen/PowerPC/fma.ll new file mode 100644 index 00000000000..0e10ad3b2ff --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fma.ll @@ -0,0 +1,46 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | egrep 'fn?madd|fn?msub' | wc -l | grep 8 + +double %test_FMADD1(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = add double %D, %C + ret double %E +} +double %test_FMADD2(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = add double %D, %C + ret double %E +} +double %test_FMSUB(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = sub double %D, %C + ret double %E +} +double %test_FNMADD1(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = add double %D, %C + %F = sub double -0.0, %E + ret double %F +} +double %test_FNMADD2(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = add double %C, %D + %F = sub double -0.0, %E + ret double %F +} +double %test_FNMSUB1(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = sub double %C, %D + ret double %E +} +double %test_FNMSUB2(double %A, double %B, double %C) { + %D = mul double %A, %B + %E = sub double %D, %C + %F = sub double -0.0, %E + ret double %F +} +float %test_FNMSUBS(float %A, float %B, float %C) { + %D = mul float %A, %B + %E = sub float %D, %C + %F = sub float -0.0, %E + ret float %F +} diff --git a/llvm/test/CodeGen/PowerPC/fnabs.ll b/llvm/test/CodeGen/PowerPC/fnabs.ll new file mode 100644 index 00000000000..5d0ef5f66d2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fnabs.ll @@ -0,0 +1,11 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep fnabs + +declare double %fabs(double) + +implementation + +double %test(double %X) { + %Y = call double %fabs(double %X) + %Z = sub double -0.0, %Y + ret double %Z +} diff --git a/llvm/test/CodeGen/PowerPC/fnegsel.ll b/llvm/test/CodeGen/PowerPC/fnegsel.ll new file mode 100644 index 00000000000..b1b06453aa1 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fnegsel.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep fneg + +double %test_FNEG_sel(double %A, double %B, double %C) { + %D = sub double -0.0, %A + %Cond = setgt double %D, -0.0 + %E = select bool %Cond, double %B, double %C + ret double %E +} diff --git a/llvm/test/CodeGen/PowerPC/fold-li.ll b/llvm/test/CodeGen/PowerPC/fold-li.ll new file mode 100644 index 00000000000..d3647753bc3 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fold-li.ll @@ -0,0 +1,14 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep -v align | not grep li + +;; Test that immediates are folded into these instructions correctly. + +int %ADD(int %X) { + %Y = add int %X, 65537 + ret int %Y +} + +int %SUB(int %X) { + %Y = sub int %X, 65537 + ret int %Y +} diff --git a/llvm/test/CodeGen/PowerPC/fp-branch.ll b/llvm/test/CodeGen/PowerPC/fp-branch.ll new file mode 100644 index 00000000000..1a371ed09a9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fp-branch.ll @@ -0,0 +1,20 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep fcmp | wc -l | grep 1 + +declare bool %llvm.isunordered.f64(double, double) + +bool %intcoord_cond_next55(double %tmp48.reload) { +newFuncRoot: + br label %cond_next55 + +bb72.exitStub: ; preds = %cond_next55 + ret bool true + +cond_next62.exitStub: ; preds = %cond_next55 + ret bool false + +cond_next55: ; preds = %newFuncRoot + %tmp57 = setge double %tmp48.reload, 1.000000e+00 ; <bool> [#uses=1] + %tmp58 = tail call bool %llvm.isunordered.f64( double %tmp48.reload, double 1.000000e+00 ) ; <bool> [#uses=1] + %tmp59 = or bool %tmp57, %tmp58 ; <bool> [#uses=1] + br bool %tmp59, label %bb72.exitStub, label %cond_next62.exitStub +} diff --git a/llvm/test/CodeGen/PowerPC/fp-int-fp.ll b/llvm/test/CodeGen/PowerPC/fp-int-fp.ll new file mode 100644 index 00000000000..bcea406ab71 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fp-int-fp.ll @@ -0,0 +1,27 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep r1 + +double %test1(double %X) { + %Y = cast double %X to long + %Z = cast long %Y to double + ret double %Z +} + +float %test2(double %X) { + %Y = cast double %X to long + %Z = cast long %Y to float + ret float %Z +} + +double %test3(float %X) { + %Y = cast float %X to long + %Z = cast long %Y to double + ret double %Z +} + +float %test4(float %X) { + %Y = cast float %X to long + %Z = cast long %Y to float + ret float %Z +} + diff --git a/llvm/test/CodeGen/PowerPC/fp_to_uint.ll b/llvm/test/CodeGen/PowerPC/fp_to_uint.ll new file mode 100644 index 00000000000..83468a42b86 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fp_to_uint.ll @@ -0,0 +1,9 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep fctiwz | wc -l | grep 1 + +implementation + +ushort %foo(float %a) { +entry: + %tmp.1 = cast float %a to ushort + ret ushort %tmp.1 +} diff --git a/llvm/test/CodeGen/PowerPC/fpcopy.ll b/llvm/test/CodeGen/PowerPC/fpcopy.ll new file mode 100644 index 00000000000..43087bd56dc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fpcopy.ll @@ -0,0 +1,7 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep fmr + +double %test(float %F) { + %F = cast float %F to double + ret double %F +} diff --git a/llvm/test/CodeGen/PowerPC/fsqrt.ll b/llvm/test/CodeGen/PowerPC/fsqrt.ll new file mode 100644 index 00000000000..1bccea34c94 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fsqrt.ll @@ -0,0 +1,13 @@ +; fsqrt should be generated when the fsqrt feature is enabled, but not +; otherwise. + +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | grep 'fsqrt f1, f1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | grep 'fsqrt f1, f1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | not grep 'fsqrt f1, f1' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | not grep 'fsqrt f1, f1' + +declare double %llvm.sqrt.f64(double) +double %X(double %Y) { + %Z = call double %llvm.sqrt.f64(double %Y) + ret double %Z +} diff --git a/llvm/test/CodeGen/PowerPC/i64_fp.ll b/llvm/test/CodeGen/PowerPC/i64_fp.ll new file mode 100644 index 00000000000..0c76bbd2eea --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/i64_fp.ll @@ -0,0 +1,17 @@ +; fcfid and fctid should be generated when the 64bit feature is enabled, but not +; otherwise. + +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mattr=+64bit | grep 'fcfid' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mattr=+64bit | grep 'fctidz' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep 'fcfid' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep 'fctidz' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mattr=-64bit | not grep 'fcfid' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mattr=-64bit | not grep 'fctidz' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g4 | not grep 'fcfid' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g4 | not grep 'fctidz' + +double %X(double %Y) { + %A = cast double %Y to long + %B = cast long %A to double + ret double %B +} diff --git a/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll b/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll new file mode 100644 index 00000000000..8b6aa3331a4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/inlineasm-copy.ll @@ -0,0 +1,14 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep mr + +int %test(int %Y, int %X) { +entry: + %tmp = tail call int asm "foo $0", "=r"( ) ; <int> [#uses=1] + ret int %tmp +} + +int %test2(int %Y, int %X) { +entry: + %tmp1 = tail call int asm "foo $0, $1", "=r,r"( int %X ) ; <int> [#uses=1] + ret int %tmp1 +} diff --git a/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll b/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll new file mode 100644 index 00000000000..6c5c288a2bc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/inverted-bool-compares.ll @@ -0,0 +1,11 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep xori && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 + +int %test(bool %B, int* %P) { + br bool %B, label %T, label %F +T: + store int 123, int* %P + ret int 0 +F: +ret int 17 +} diff --git a/llvm/test/CodeGen/PowerPC/lha.ll b/llvm/test/CodeGen/PowerPC/lha.ll new file mode 100644 index 00000000000..cc35e8ab9e9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/lha.ll @@ -0,0 +1,7 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep lha + +uint %test(short* %a) { + %tmp.1 = load short* %a + %tmp.2 = cast short %tmp.1 to uint + ret uint %tmp.2 +} diff --git a/llvm/test/CodeGen/PowerPC/load-constant-addr.ll b/llvm/test/CodeGen/PowerPC/load-constant-addr.ll new file mode 100644 index 00000000000..d7e3d454e4e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/load-constant-addr.ll @@ -0,0 +1,9 @@ +; Should fold the ori into the lfs. +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep lfs && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep ori + +float %test() { + %tmp.i = load float* cast (uint 186018016 to float*) + ret float %tmp.i +} + diff --git a/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll new file mode 100644 index 00000000000..5d8a3a1a016 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll @@ -0,0 +1,17 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep 'li.*16' && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep addi + +; Codegen lvx (R+16) as t = li 16, lvx t,R +; This shares the 16 between the two loads. + +void %func(<4 x float>* %a, <4 x float>* %b) { + %tmp1 = getelementptr <4 x float>* %b, int 1 + %tmp = load <4 x float>* %tmp1 + %tmp3 = getelementptr <4 x float>* %a, int 1 + %tmp4 = load <4 x float>* %tmp3 + %tmp5 = mul <4 x float> %tmp, %tmp4 + %tmp8 = load <4 x float>* %b + %tmp9 = add <4 x float> %tmp5, %tmp8 + store <4 x float> %tmp9, <4 x float>* %a + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/mem_update.ll b/llvm/test/CodeGen/PowerPC/mem_update.ll new file mode 100644 index 00000000000..2a8f83fbd36 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mem_update.ll @@ -0,0 +1,68 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -enable-ppc-preinc && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -enable-ppc-preinc | not grep addi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -enable-ppc-preinc && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc64 -enable-ppc-preinc | not grep addi +%Glob = global ulong 4 + +int *%test0(int *%X, int *%dest) { + %Y = getelementptr int* %X, int 4 + %A = load int* %Y + store int %A, int* %dest + ret int* %Y +} + +int *%test1(int *%X, int *%dest) { + %Y = getelementptr int* %X, int 4 + %A = load int* %Y + store int %A, int* %dest + ret int* %Y +} + +short *%test2(short *%X, int *%dest) { + %Y = getelementptr short* %X, int 4 + %A = load short* %Y + %B = cast short %A to int + store int %B, int* %dest + ret short* %Y +} + +ushort *%test3(ushort *%X, int *%dest) { + %Y = getelementptr ushort* %X, int 4 + %A = load ushort* %Y + %B = cast ushort %A to int + store int %B, int* %dest + ret ushort* %Y +} + +short *%test3a(short *%X, long *%dest) { + %Y = getelementptr short* %X, int 4 + %A = load short* %Y + %B = cast short %A to long + store long %B, long* %dest + ret short* %Y +} + +long *%test4(long *%X, long *%dest) { + %Y = getelementptr long* %X, int 4 + %A = load long* %Y + store long %A, long* %dest + ret long* %Y +} + +ushort *%test5(ushort *%X) { + %Y = getelementptr ushort* %X, int 4 + store ushort 7, ushort* %Y + ret ushort* %Y +} + +ulong *%test6(ulong *%X, ulong %A) { + %Y = getelementptr ulong* %X, int 4 + store ulong %A, ulong* %Y + ret ulong* %Y +} + +ulong *%test7(ulong *%X, ulong %A) { + store ulong %A, ulong* %Glob + ret ulong *%Glob +} + diff --git a/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll b/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll new file mode 100644 index 00000000000..cb1f46c672d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mul-neg-power-2.ll @@ -0,0 +1,9 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep mul + +int %test1(int %a) { + %tmp.1 = mul int %a, -2 ; <int> [#uses=1] + %tmp.2 = add int %tmp.1, 63 ; <int> [#uses=1] + ret int %tmp.2 +} + diff --git a/llvm/test/CodeGen/PowerPC/mulhs.ll b/llvm/test/CodeGen/PowerPC/mulhs.ll new file mode 100644 index 00000000000..e5e25e99f44 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mulhs.ll @@ -0,0 +1,17 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep mulhwu && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srawi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep add && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep mulhw | wc -l | grep 1 + +implementation ; Functions: + +int %mulhs(int %a, int %b) { +entry: + %tmp.1 = cast int %a to ulong ; <ulong> [#uses=1] + %tmp.3 = cast int %b to ulong ; <ulong> [#uses=1] + %tmp.4 = mul ulong %tmp.3, %tmp.1 ; <ulong> [#uses=1] + %tmp.6 = shr ulong %tmp.4, ubyte 32 ; <ulong> [#uses=1] + %tmp.7 = cast ulong %tmp.6 to int ; <int> [#uses=1] + ret int %tmp.7 +} diff --git a/llvm/test/CodeGen/PowerPC/neg.ll b/llvm/test/CodeGen/PowerPC/neg.ll new file mode 100644 index 00000000000..7119f6c0da9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/neg.ll @@ -0,0 +1,6 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep neg + +int %test(int %X) { + %Y = sub int 0, %X + ret int %Y +} diff --git a/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll b/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll new file mode 100644 index 00000000000..9c1d949505a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/or-addressing-mode.ll @@ -0,0 +1,23 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc && +; RUN: llvm-upgrade < %s | llvm-as | llc | not grep ori && +; RUN: llvm-upgrade < %s | llvm-as | llc | not grep rlwimi + +int %test1(sbyte* %P) { ;; or -> lwzx + %tmp.2.i = cast sbyte* %P to uint + %tmp.4.i = and uint %tmp.2.i, 4294901760 + %tmp.10.i = shr uint %tmp.2.i, ubyte 5 + %tmp.11.i = and uint %tmp.10.i, 2040 + %tmp.13.i = or uint %tmp.11.i, %tmp.4.i + %tmp.14.i = cast uint %tmp.13.i to int* + %tmp.3 = load int* %tmp.14.i + ret int %tmp.3 +} + +int %test2(int %P) { ;; or -> lwz + %tmp.2 = shl int %P, ubyte 4 + %tmp.3 = or int %tmp.2, 2 + %tmp.4 = cast int %tmp.3 to int* + %tmp.5 = load int* %tmp.4 + ret int %tmp.5 +} + diff --git a/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll new file mode 100644 index 00000000000..5f3049d221d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/reg-coalesce-simple.ll @@ -0,0 +1,12 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep or + +%struct.foo = type { int, int, [0 x ubyte] } +int %test(%struct.foo* %X) { + %tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100 + %tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1] + %tmp2 = cast ubyte %tmp to int ; <int> [#uses=1] + ret int %tmp2} + + + diff --git a/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll b/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll new file mode 100644 index 00000000000..4b2b07f3350 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rlwimi-commute.ll @@ -0,0 +1,26 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwimi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep 'or ' + +; Make sure there is no register-register copies here. + +void %test1(int *%A, int *%B, int *%D, int* %E) { + %A = load int* %A + %B = load int* %B + %X = and int %A, 15 + %Y = and int %B, -16 + %Z = or int %X, %Y + store int %Z, int* %D + store int %A, int* %E + ret void +} + +void %test2(int *%A, int *%B, int *%D, int* %E) { + %A = load int* %A + %B = load int* %B + %X = and int %A, 15 + %Y = and int %B, -16 + %Z = or int %X, %Y + store int %Z, int* %D + store int %B, int* %E + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/rlwimi.ll b/llvm/test/CodeGen/PowerPC/rlwimi.ll new file mode 100644 index 00000000000..3b5816b5a0e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rlwimi.ll @@ -0,0 +1,72 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep and && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwimi | wc -l | grep 8 + +implementation ; Functions: + +int %test1(int %x, int %y) { +entry: + %tmp.3 = shl int %x, ubyte 16 ; <int> [#uses=1] + %tmp.7 = and int %y, 65535 ; <int> [#uses=1] + %tmp.9 = or int %tmp.7, %tmp.3 ; <int> [#uses=1] + ret int %tmp.9 +} + +int %test2(int %x, int %y) { +entry: + %tmp.7 = and int %x, 65535 ; <int> [#uses=1] + %tmp.3 = shl int %y, ubyte 16 ; <int> [#uses=1] + %tmp.9 = or int %tmp.7, %tmp.3 ; <int> [#uses=1] + ret int %tmp.9 +} + +uint %test3(uint %x, uint %y) { +entry: + %tmp.3 = shr uint %x, ubyte 16 ; <uint> [#uses=1] + %tmp.6 = and uint %y, 4294901760 ; <uint> [#uses=1] + %tmp.7 = or uint %tmp.6, %tmp.3 ; <uint> [#uses=1] + ret uint %tmp.7 +} + +uint %test4(uint %x, uint %y) { +entry: + %tmp.6 = and uint %x, 4294901760 ; <uint> [#uses=1] + %tmp.3 = shr uint %y, ubyte 16 ; <uint> [#uses=1] + %tmp.7 = or uint %tmp.6, %tmp.3 ; <uint> [#uses=1] + ret uint %tmp.7 +} + +int %test5(int %x, int %y) { +entry: + %tmp.3 = shl int %x, ubyte 1 ; <int> [#uses=1] + %tmp.4 = and int %tmp.3, -65536 ; <int> [#uses=1] + %tmp.7 = and int %y, 65535 ; <int> [#uses=1] + %tmp.9 = or int %tmp.4, %tmp.7 ; <int> [#uses=1] + ret int %tmp.9 +} + +int %test6(int %x, int %y) { +entry: + %tmp.7 = and int %x, 65535 ; <int> [#uses=1] + %tmp.3 = shl int %y, ubyte 1 ; <int> [#uses=1] + %tmp.4 = and int %tmp.3, -65536 ; <int> [#uses=1] + %tmp.9 = or int %tmp.4, %tmp.7 ; <int> [#uses=1] + ret int %tmp.9 +} + +int %test7(int %x, int %y) { +entry: + %tmp.2 = and int %x, -65536 ; <int> [#uses=1] + %tmp.5 = and int %y, 65535 ; <int> [#uses=1] + %tmp.7 = or int %tmp.5, %tmp.2 ; <int> [#uses=1] + ret int %tmp.7 +} + +uint %test8(uint %bar) { +entry: + %tmp.3 = shl uint %bar, ubyte 1 ; <uint> [#uses=1] + %tmp.4 = and uint %tmp.3, 2 ; <uint> [#uses=1] + %tmp.6 = and uint %bar, 4294967293 ; <uint> [#uses=1] + %tmp.7 = or uint %tmp.4, %tmp.6 ; <uint> [#uses=1] + ret uint %tmp.7 +} diff --git a/llvm/test/CodeGen/PowerPC/rlwimi2.ll b/llvm/test/CodeGen/PowerPC/rlwimi2.ll new file mode 100644 index 00000000000..966705dcffb --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rlwimi2.ll @@ -0,0 +1,30 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwimi | wc -l | grep 3 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep srwi | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep slwi + +implementation ; Functions: + +ushort %test1(uint %srcA, uint %srcB, uint %alpha) { +entry: + %tmp.1 = shl uint %srcA, ubyte 15 ; <uint> [#uses=1] + %tmp.4 = and uint %tmp.1, 32505856 ; <uint> [#uses=1] + %tmp.6 = and uint %srcA, 31775 ; <uint> [#uses=1] + %tmp.7 = or uint %tmp.4, %tmp.6 ; <uint> [#uses=1] + %tmp.9 = shl uint %srcB, ubyte 15 ; <uint> [#uses=1] + %tmp.12 = and uint %tmp.9, 32505856 ; <uint> [#uses=1] + %tmp.14 = and uint %srcB, 31775 ; <uint> [#uses=1] + %tmp.15 = or uint %tmp.12, %tmp.14 ; <uint> [#uses=1] + %tmp.18 = mul uint %tmp.7, %alpha ; <uint> [#uses=1] + %tmp.20 = sub uint 32, %alpha ; <uint> [#uses=1] + %tmp.22 = mul uint %tmp.15, %tmp.20 ; <uint> [#uses=1] + %tmp.23 = add uint %tmp.22, %tmp.18 ; <uint> [#uses=2] + %tmp.27 = shr uint %tmp.23, ubyte 5 ; <uint> [#uses=1] + %tmp.28 = cast uint %tmp.27 to ushort ; <ushort> [#uses=1] + %tmp.29 = and ushort %tmp.28, 31775 ; <ushort> [#uses=1] + %tmp.33 = shr uint %tmp.23, ubyte 20 ; <uint> [#uses=1] + %tmp.34 = cast uint %tmp.33 to ushort ; <ushort> [#uses=1] + %tmp.35 = and ushort %tmp.34, 992 ; <ushort> [#uses=1] + %tmp.36 = or ushort %tmp.29, %tmp.35 ; <ushort> [#uses=1] + ret ushort %tmp.36 +} diff --git a/llvm/test/CodeGen/PowerPC/rlwimi3.ll b/llvm/test/CodeGen/PowerPC/rlwimi3.ll new file mode 100644 index 00000000000..44bc034237c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rlwimi3.ll @@ -0,0 +1,25 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -stats 2>&1 | grep 'Number of machine instrs printed' | grep 12 + +ushort %Trans16Bit(uint %srcA, uint %srcB, uint %alpha) { + %tmp1 = shl uint %srcA, ubyte 15 ; <uint> [#uses=1] + %tmp2 = and uint %tmp1, 32505856 ; <uint> [#uses=1] + %tmp4 = and uint %srcA, 31775 ; <uint> [#uses=1] + %tmp5 = or uint %tmp2, %tmp4 ; <uint> [#uses=1] + %tmp7 = shl uint %srcB, ubyte 15 ; <uint> [#uses=1] + %tmp8 = and uint %tmp7, 32505856 ; <uint> [#uses=1] + %tmp10 = and uint %srcB, 31775 ; <uint> [#uses=1] + %tmp11 = or uint %tmp8, %tmp10 ; <uint> [#uses=1] + %tmp14 = mul uint %tmp5, %alpha ; <uint> [#uses=1] + %tmp16 = sub uint 32, %alpha ; <uint> [#uses=1] + %tmp18 = mul uint %tmp11, %tmp16 ; <uint> [#uses=1] + %tmp19 = add uint %tmp18, %tmp14 ; <uint> [#uses=2] + %tmp21 = shr uint %tmp19, ubyte 5 ; <uint> [#uses=1] + %tmp21 = cast uint %tmp21 to ushort ; <ushort> [#uses=1] + %tmp = and ushort %tmp21, 31775 ; <ushort> [#uses=1] + %tmp23 = shr uint %tmp19, ubyte 20 ; <uint> [#uses=1] + %tmp23 = cast uint %tmp23 to ushort ; <ushort> [#uses=1] + %tmp24 = and ushort %tmp23, 992 ; <ushort> [#uses=1] + %tmp25 = or ushort %tmp, %tmp24 ; <ushort> [#uses=1] + ret ushort %tmp25 +} + diff --git a/llvm/test/CodeGen/PowerPC/rlwinm.ll b/llvm/test/CodeGen/PowerPC/rlwinm.ll new file mode 100644 index 00000000000..45f26d77dd8 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rlwinm.ll @@ -0,0 +1,63 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep and && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srawi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srwi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep slwi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwinm | wc -l | grep 8 + +implementation ; Functions: + +int %test1(int %a) { +entry: + %tmp.1 = and int %a, 268431360 ; <int> [#uses=1] + ret int %tmp.1 +} + +int %test2(int %a) { +entry: + %tmp.1 = and int %a, -268435441 ; <int> [#uses=1] + ret int %tmp.1 +} + +int %test3(int %a) { +entry: + %tmp.2 = shr int %a, ubyte 8 ; <int> [#uses=1] + %tmp.3 = and int %tmp.2, 255 ; <int> [#uses=1] + ret int %tmp.3 +} + +uint %test4(uint %a) { +entry: + %tmp.3 = shr uint %a, ubyte 8 ; <uint> [#uses=1] + %tmp.4 = and uint %tmp.3, 255 ; <uint> [#uses=1] + ret uint %tmp.4 +} + +int %test5(int %a) { +entry: + %tmp.2 = shl int %a, ubyte 8 ; <int> [#uses=1] + %tmp.3 = and int %tmp.2, -8388608 ; <int> [#uses=1] + ret int %tmp.3 +} + +int %test6(int %a) { +entry: + %tmp.1 = and int %a, 65280 ; <int> [#uses=1] + %tmp.2 = shr int %tmp.1, ubyte 8 ; <uint> [#uses=1] + ret int %tmp.2 +} + +uint %test7(uint %a) { +entry: + %tmp.1 = and uint %a, 65280 ; <uint> [#uses=1] + %tmp.2 = shr uint %tmp.1, ubyte 8 ; <uint> [#uses=1] + ret uint %tmp.2 +} + +int %test8(int %a) { +entry: + %tmp.1 = and int %a, 16711680 ; <int> [#uses=1] + %tmp.2 = shl int %tmp.1, ubyte 8 ; <int> [#uses=1] + ret int %tmp.2 +} + diff --git a/llvm/test/CodeGen/PowerPC/rlwinm2.ll b/llvm/test/CodeGen/PowerPC/rlwinm2.ll new file mode 100644 index 00000000000..70ad636e3bd --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rlwinm2.ll @@ -0,0 +1,30 @@ +; All of these ands and shifts should be folded into rlw[i]nm instructions +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep and && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srawi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep srwi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep slwi && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwnm | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep rlwinm | wc -l | grep 1 + + +implementation ; Functions: + +uint %test1(uint %X, int %Y) { +entry: + %tmp = cast int %Y to ubyte ; <ubyte> [#uses=2] + %tmp1 = shl uint %X, ubyte %tmp ; <uint> [#uses=1] + %tmp2 = sub ubyte 32, %tmp ; <ubyte> [#uses=1] + %tmp3 = shr uint %X, ubyte %tmp2 ; <uint> [#uses=1] + %tmp4 = or uint %tmp1, %tmp3 ; <uint> [#uses=1] + %tmp6 = and uint %tmp4, 127 ; <uint> [#uses=1] + ret uint %tmp6 +} + +uint %test2(uint %X) { +entry: + %tmp1 = shr uint %X, ubyte 27 ; <uint> [#uses=1] + %tmp2 = shl uint %X, ubyte 5 ; <uint> [#uses=1] + %tmp2.masked = and uint %tmp2, 96 ; <uint> [#uses=1] + %tmp5 = or uint %tmp1, %tmp2.masked ; <uint> [#uses=1] + ret uint %tmp5 +} diff --git a/llvm/test/CodeGen/PowerPC/rotl.ll b/llvm/test/CodeGen/PowerPC/rotl.ll new file mode 100644 index 00000000000..aeb59aab556 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/rotl.ll @@ -0,0 +1,53 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep or && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | \ +; RUN: grep rlwnm | wc -l | grep 2 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | \ +; RUN: grep rlwinm | wc -l | grep 2 + +implementation ; Functions: + +int %rotlw(uint %x, int %sh) { +entry: + %tmp.3 = cast int %sh to ubyte ; <ubyte> [#uses=1] + %x = cast uint %x to int ; <int> [#uses=1] + %tmp.7 = sub int 32, %sh ; <int> [#uses=1] + %tmp.9 = cast int %tmp.7 to ubyte ; <ubyte> [#uses=1] + %tmp.10 = shr uint %x, ubyte %tmp.9 ; <uint> [#uses=1] + %tmp.4 = shl int %x, ubyte %tmp.3 ; <int> [#uses=1] + %tmp.10 = cast uint %tmp.10 to int ; <int> [#uses=1] + %tmp.12 = or int %tmp.10, %tmp.4 ; <int> [#uses=1] + ret int %tmp.12 +} + +int %rotrw(uint %x, int %sh) { +entry: + %tmp.3 = cast int %sh to ubyte ; <ubyte> [#uses=1] + %tmp.4 = shr uint %x, ubyte %tmp.3 ; <uint> [#uses=1] + %tmp.7 = sub int 32, %sh ; <int> [#uses=1] + %tmp.9 = cast int %tmp.7 to ubyte ; <ubyte> [#uses=1] + %x = cast uint %x to int ; <int> [#uses=1] + %tmp.4 = cast uint %tmp.4 to int ; <int> [#uses=1] + %tmp.10 = shl int %x, ubyte %tmp.9 ; <int> [#uses=1] + %tmp.12 = or int %tmp.4, %tmp.10 ; <int> [#uses=1] + ret int %tmp.12 +} + +int %rotlwi(uint %x) { +entry: + %x = cast uint %x to int ; <int> [#uses=1] + %tmp.7 = shr uint %x, ubyte 27 ; <uint> [#uses=1] + %tmp.3 = shl int %x, ubyte 5 ; <int> [#uses=1] + %tmp.7 = cast uint %tmp.7 to int ; <int> [#uses=1] + %tmp.9 = or int %tmp.3, %tmp.7 ; <int> [#uses=1] + ret int %tmp.9 +} + +int %rotrwi(uint %x) { +entry: + %tmp.3 = shr uint %x, ubyte 5 ; <uint> [#uses=1] + %x = cast uint %x to int ; <int> [#uses=1] + %tmp.3 = cast uint %tmp.3 to int ; <int> [#uses=1] + %tmp.7 = shl int %x, ubyte 27 ; <int> [#uses=1] + %tmp.9 = or int %tmp.3, %tmp.7 ; <int> [#uses=1] + ret int %tmp.9 +} diff --git a/llvm/test/CodeGen/PowerPC/select_lt0.ll b/llvm/test/CodeGen/PowerPC/select_lt0.ll new file mode 100644 index 00000000000..bb5213f946d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/select_lt0.ll @@ -0,0 +1,51 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep cmp + +int %seli32_1(int %a) { +entry: + %tmp.1 = setlt int %a, 0 + %retval = select bool %tmp.1, int 5, int 0 + ret int %retval +} + +int %seli32_2(int %a, int %b) { +entry: + %tmp.1 = setlt int %a, 0 + %retval = select bool %tmp.1, int %b, int 0 + ret int %retval +} + +int %seli32_3(int %a, short %b) { +entry: + %tmp.2 = cast short %b to int + %tmp.1 = setlt int %a, 0 + %retval = select bool %tmp.1, int %tmp.2, int 0 + ret int %retval +} + +int %seli32_4(int %a, ushort %b) { +entry: + %tmp.2 = cast ushort %b to int + %tmp.1 = setlt int %a, 0 + %retval = select bool %tmp.1, int %tmp.2, int 0 + ret int %retval +} + +short %seli16_1(short %a) { +entry: + %tmp.1 = setlt short %a, 0 + %retval = select bool %tmp.1, short 7, short 0 + ret short %retval +} + +short %seli16_2(int %a, short %b) { + %tmp.1 = setlt int %a, 0 + %retval = select bool %tmp.1, short %b, short 0 + ret short %retval +} + +int %seli32_a_a(int %a) { + %tmp = setlt int %a, 1 + %min = select bool %tmp, int %a, int 0 + ret int %min +} + diff --git a/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll b/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll new file mode 100644 index 00000000000..00e9bf0710c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep rlwinm + +int %setcc_one_or_zero(int* %a) { +entry: + %tmp.1 = setne int* %a, null + %inc.1 = cast bool %tmp.1 to int + ret int %inc.1 +} diff --git a/llvm/test/CodeGen/PowerPC/seteq-0.ll b/llvm/test/CodeGen/PowerPC/seteq-0.ll new file mode 100644 index 00000000000..ddba7f022aa --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/seteq-0.ll @@ -0,0 +1,7 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep 'srwi r., r., 5' + +int %eq0(int %a) { + %tmp.1 = seteq int %a, 0 ; <bool> [#uses=1] + %tmp.2 = cast bool %tmp.1 to int ; <int> [#uses=1] + ret int %tmp.2 +} diff --git a/llvm/test/CodeGen/PowerPC/shl_sext.ll b/llvm/test/CodeGen/PowerPC/shl_sext.ll new file mode 100644 index 00000000000..af18338f4b2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/shl_sext.ll @@ -0,0 +1,17 @@ +; This test should not contain a sign extend +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep extsb + +int %test(uint %mode.0.i.0) { + %tmp.79 = cast uint %mode.0.i.0 to sbyte ; <sbyte> [#uses=1] + %tmp.80 = cast sbyte %tmp.79 to int ; <int> [#uses=1] + %tmp.81 = shl int %tmp.80, ubyte 24 ; <int> [#uses=1] + ret int %tmp.81 +} + +int %test2(uint %mode.0.i.0) { + %tmp.79 = cast uint %mode.0.i.0 to sbyte ; <sbyte> [#uses=1] + %tmp.80 = cast sbyte %tmp.79 to int ; <int> [#uses=1] + %tmp.81 = shl int %tmp.80, ubyte 16 ; <int> [#uses=1] + %tmp.82 = and int %tmp.81, 16711680 + ret int %tmp.82 +} diff --git a/llvm/test/CodeGen/PowerPC/small-arguments.ll b/llvm/test/CodeGen/PowerPC/small-arguments.ll new file mode 100644 index 00000000000..0068427772b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/small-arguments.ll @@ -0,0 +1,53 @@ +; RUN: llvm-as < %s | llc -march=ppc32 && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep 'extsh\|rlwinm' + +declare i16 %foo() sext + +define i32 %test1(i16 sext %X) { + %Y = sext i16 %X to i32 ;; dead + ret i32 %Y +} + +define i32 %test2(i16 zext %X) { + %Y = sext i16 %X to i32 + %Z = and i32 %Y, 65535 ;; dead + ret i32 %Z +} + +define void %test3() { + %tmp.0 = call i16 %foo() sext ;; no extsh! + %tmp.1 = icmp slt i16 %tmp.0, 1234 + br i1 %tmp.1, label %then, label %UnifiedReturnBlock + +then: + call i32 %test1(i16 0 sext) + ret void +UnifiedReturnBlock: + ret void +} + +define i32 %test4(i16* %P) { + %tmp.1 = load i16* %P + %tmp.2 = zext i16 %tmp.1 to i32 + %tmp.3 = and i32 %tmp.2, 255 + ret i32 %tmp.3 +} + +define i32 %test5(i16* %P) { + %tmp.1 = load i16* %P + %tmp.2 = bitcast i16 %tmp.1 to i16 + %tmp.3 = zext i16 %tmp.2 to i32 + %tmp.4 = and i32 %tmp.3, 255 + ret i32 %tmp.4 +} + +define i32 %test6(i32* %P) { + %tmp.1 = load i32* %P + %tmp.2 = and i32 %tmp.1, 255 + ret i32 %tmp.2 +} + +define i16 %test7(float %a) zext { + %tmp.1 = fptoui float %a to i16 + ret i16 %tmp.1 +} diff --git a/llvm/test/CodeGen/PowerPC/stfiwx.ll b/llvm/test/CodeGen/PowerPC/stfiwx.ll new file mode 100644 index 00000000000..6d15787471d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/stfiwx.ll @@ -0,0 +1,21 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx | grep stfiwx && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx | not grep r1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx | not grep stfiwx && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx | grep r1 + +void %test(float %a, int* %b) { + %tmp.2 = cast float %a to int + store int %tmp.2, int* %b + ret void +} + +void %test2(float %a, int* %b, int %i) { + %tmp.2 = getelementptr int* %b, int 1 + %tmp.5 = getelementptr int* %b, int %i + %tmp.7 = cast float %a to int + store int %tmp.7, int* %tmp.5 + store int %tmp.7, int* %tmp.2 + store int %tmp.7, int* %b + ret void +} + diff --git a/llvm/test/CodeGen/PowerPC/store-load-fwd.ll b/llvm/test/CodeGen/PowerPC/store-load-fwd.ll new file mode 100644 index 00000000000..d4a8a543d19 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/store-load-fwd.ll @@ -0,0 +1,7 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | not grep lwz +int %test(int* %P) { + store int 1, int* %P + %V = load int* %P + ret int %V +} diff --git a/llvm/test/CodeGen/PowerPC/subc.ll b/llvm/test/CodeGen/PowerPC/subc.ll new file mode 100644 index 00000000000..36e1c0a3703 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/subc.ll @@ -0,0 +1,25 @@ +; All of these should be codegen'd without loading immediates +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep subfc | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep subfe | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep subfze | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep subfme | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 | grep subfic | wc -l | grep 2 +implementation ; Functions: + +long %sub_ll(long %a, long %b) { +entry: + %tmp.2 = sub long %a, %b ; <long> [#uses=1] + ret long %tmp.2 +} + +long %sub_l_5(long %a) { +entry: + %tmp.1 = sub long 5, %a ; <long> [#uses=1] + ret long %tmp.1 +} + +long %sub_l_m5(long %a) { +entry: + %tmp.1 = sub long -5, %a ; <long> [#uses=1] + ret long %tmp.1 +} diff --git a/llvm/test/CodeGen/PowerPC/unsafe-math.ll b/llvm/test/CodeGen/PowerPC/unsafe-math.ll new file mode 100644 index 00000000000..29a45985bb0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/unsafe-math.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep fmul | wc -l | grep 2 && +; RUN: llvm-as < %s | llc -march=ppc32 -enable-unsafe-fp-math | grep fmul | wc -l | grep 1 + +define double %foo(double %X) { + %tmp1 = mul double %X, 1.23 + %tmp2 = mul double %tmp1, 4.124 + ret double %tmp2 +} + diff --git a/llvm/test/CodeGen/PowerPC/vcmp-fold.ll b/llvm/test/CodeGen/PowerPC/vcmp-fold.ll new file mode 100644 index 00000000000..6ae41a980c9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vcmp-fold.ll @@ -0,0 +1,21 @@ +; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single +; "vcmpbfp.". +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vcmpbfp | wc -l | grep 1 + +void %test(<4 x float>* %x, <4 x float>* %y, int* %P) { +entry: + %tmp = load <4 x float>* %x ; <<4 x float>> [#uses=1] + %tmp2 = load <4 x float>* %y ; <<4 x float>> [#uses=1] + %tmp = call int %llvm.ppc.altivec.vcmpbfp.p( int 1, <4 x float> %tmp, <4 x float> %tmp2 ) ; <int> [#uses=1] + %tmp4 = load <4 x float>* %x ; <<4 x float>> [#uses=1] + %tmp6 = load <4 x float>* %y ; <<4 x float>> [#uses=1] + %tmp = call <4 x int> %llvm.ppc.altivec.vcmpbfp( <4 x float> %tmp4, <4 x float> %tmp6 ) ; <<4 x int>> [#uses=1] + %tmp7 = cast <4 x int> %tmp to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp7, <4 x float>* %x + store int %tmp, int* %P + ret void +} + +declare int %llvm.ppc.altivec.vcmpbfp.p(int, <4 x float>, <4 x float>) + +declare <4 x int> %llvm.ppc.altivec.vcmpbfp(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll b/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll new file mode 100644 index 00000000000..62a9552f080 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_br_cmp.ll @@ -0,0 +1,22 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vcmpeqfp. && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep mfcr + +; A predicate compare used immediately by a branch should not generate an mfcr. + +void %test(<4 x float>* %A, <4 x float>* %B) { + %tmp = load <4 x float>* %A + %tmp3 = load <4 x float>* %B + %tmp = tail call int %llvm.ppc.altivec.vcmpeqfp.p( int 1, <4 x float> %tmp, <4 x float> %tmp3 ) + %tmp = seteq int %tmp, 0 + br bool %tmp, label %cond_true, label %UnifiedReturnBlock + +cond_true: + store <4 x float> zeroinitializer, <4 x float>* %B + ret void + +UnifiedReturnBlock: + ret void +} + +declare int %llvm.ppc.altivec.vcmpeqfp.p(int, <4 x float>, <4 x float>) + diff --git a/llvm/test/CodeGen/PowerPC/vec_call.ll b/llvm/test/CodeGen/PowerPC/vec_call.ll new file mode 100644 index 00000000000..b2b91fe3f45 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_call.ll @@ -0,0 +1,11 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 + +<4 x int> %test_arg(<4 x int> %A, <4 x int> %B) { + %C = add <4 x int> %A, %B + ret <4 x int> %C +} + +<4 x int> %foo() { + %X = call <4 x int> %test_arg(<4 x int> zeroinitializer, <4 x int> zeroinitializer) + ret <4 x int> %X +} diff --git a/llvm/test/CodeGen/PowerPC/vec_constants.ll b/llvm/test/CodeGen/PowerPC/vec_constants.ll new file mode 100644 index 00000000000..9d51e3c6821 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_constants.ll @@ -0,0 +1,48 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep CPI + + +; Tests spltw(0x80000000) and spltw(0x7FFFFFFF). +void %test1(<4 x int>* %P1, <4 x int>* %P2, <4 x float>* %P3) { + %tmp = load <4 x int>* %P1 + %tmp4 = and <4 x int> %tmp, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 > + store <4 x int> %tmp4, <4 x int>* %P1 + %tmp7 = load <4 x int>* %P2 + %tmp9 = and <4 x int> %tmp7, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 > + store <4 x int> %tmp9, <4 x int>* %P2 + %tmp = load <4 x float>* %P3 + %tmp11 = cast <4 x float> %tmp to <4 x int> + %tmp12 = and <4 x int> %tmp11, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 > + %tmp13 = cast <4 x int> %tmp12 to <4 x float> + store <4 x float> %tmp13, <4 x float>* %P3 + ret void +} + +<4 x int> %test_30() { + ret <4 x int> <int 30, int 30, int 30, int 30> +} + +<4 x int> %test_29() { + ret <4 x int> <int 29, int 29, int 29, int 29> +} + +<8 x short> %test_n30() { + ret <8 x short> <short -30, short -30, short -30, short -30, + short -30, short -30, short -30, short -30> +} + +<16 x sbyte> %test_n104() { + ret <16 x sbyte> <sbyte -104, sbyte -104, sbyte -104, sbyte -104, + sbyte -104, sbyte -104, sbyte -104, sbyte -104, + sbyte -104, sbyte -104, sbyte -104, sbyte -104, + sbyte -104, sbyte -104, sbyte -104, sbyte -104> +} + +<4 x int> %test_vsldoi() { + ret <4 x int> <int 512, int 512, int 512, int 512> +} + +<4 x int> %test_rol() { + ret <4 x int> <int -11534337, int -11534337, int -11534337, int -11534337> +} + diff --git a/llvm/test/CodeGen/PowerPC/vec_mul.ll b/llvm/test/CodeGen/PowerPC/vec_mul.ll new file mode 100644 index 00000000000..1f571f44867 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_mul.ll @@ -0,0 +1,25 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep mullw && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vmsumuhm + +<4 x int> %test_v4i32(<4 x int>* %X, <4 x int>* %Y) { + %tmp = load <4 x int>* %X + %tmp2 = load <4 x int>* %Y + %tmp3 = mul <4 x int> %tmp, %tmp2 + ret <4 x int> %tmp3 +} + +<8 x short> %test_v8i16(<8 x short>* %X, <8 x short>* %Y) { + %tmp = load <8 x short>* %X + %tmp2 = load <8 x short>* %Y + %tmp3 = mul <8 x short> %tmp, %tmp2 + ret <8 x short> %tmp3 +} + +<16 x sbyte> %test_v16i8(<16 x sbyte>* %X, <16 x sbyte>* %Y) { + %tmp = load <16 x sbyte>* %X + %tmp2 = load <16 x sbyte>* %Y + %tmp3 = mul <16 x sbyte> %tmp, %tmp2 + ret <16 x sbyte> %tmp3 +} + diff --git a/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll new file mode 100644 index 00000000000..4f67f83f7e3 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll @@ -0,0 +1,43 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm + +<4 x float> %test_uu72(<4 x float> *%P1, <4 x float> *%P2) { + %V1 = load <4 x float> *%P1 + %V2 = load <4 x float> *%P2 + ; vmrglw + vsldoi + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, + <4 x uint> <uint undef, uint undef, uint 7, uint 2> + ret <4 x float> %V3 +} + +<4 x float> %test_30u5(<4 x float> *%P1, <4 x float> *%P2) { + %V1 = load <4 x float> *%P1 + %V2 = load <4 x float> *%P2 + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, + <4 x uint> <uint 3, uint 0, uint undef, uint 5> + ret <4 x float> %V3 +} + +<4 x float> %test_3u73(<4 x float> *%P1, <4 x float> *%P2) { + %V1 = load <4 x float> *%P1 + %V2 = load <4 x float> *%P2 + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, + <4 x uint> <uint 3, uint undef, uint 7, uint 3> + ret <4 x float> %V3 +} + +<4 x float> %test_3774(<4 x float> *%P1, <4 x float> *%P2) { + %V1 = load <4 x float> *%P1 + %V2 = load <4 x float> *%P2 + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, + <4 x uint> <uint 3, uint 7, uint 7, uint 4> + ret <4 x float> %V3 +} + +<4 x float> %test_4450(<4 x float> *%P1, <4 x float> *%P2) { + %V1 = load <4 x float> *%P1 + %V2 = load <4 x float> *%P2 + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, + <4 x uint> <uint 4, uint 4, uint 5, uint 0> + ret <4 x float> %V3 +} diff --git a/llvm/test/CodeGen/PowerPC/vec_shuffle.ll b/llvm/test/CodeGen/PowerPC/vec_shuffle.ll new file mode 100644 index 00000000000..8e64aacb943 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_shuffle.ll @@ -0,0 +1,504 @@ +; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 7 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 6 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vpkuhum | wc -l | grep 1 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vpkuwum | wc -l | grep 1 + +void %VSLDOI_xy(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=1] + %tmp = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=11] + %tmp2 = cast <8 x short> %tmp2 to <16 x sbyte> ; <<16 x sbyte>> [#uses=5] + %tmp = extractelement <16 x sbyte> %tmp, uint 5 ; <sbyte> [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 6 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 7 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 8 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 9 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 10 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 12 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 13 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 14 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 15 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 0 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp2, uint 1 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 2 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp2, uint 3 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 4 ; <sbyte> [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + %tmp33 = cast <16 x sbyte> %tmp33 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp33, <8 x short>* %A + ret void +} + +void %VSLDOI_xx(<8 x short>* %A, <8 x short>* %B) { + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp2 = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=11] + %tmp2 = cast <8 x short> %tmp2 to <16 x sbyte> ; <<16 x sbyte>> [#uses=5] + %tmp = extractelement <16 x sbyte> %tmp, uint 5 ; <sbyte> [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 6 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 7 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 8 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 9 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 10 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 12 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 13 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 14 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 15 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 0 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp2, uint 1 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 2 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp2, uint 3 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 4 ; <sbyte> [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + %tmp33 = cast <16 x sbyte> %tmp33 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp33, <8 x short>* %A + ret void +} + +void %VPERM_promote(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=1] + %tmp = cast <8 x short> %tmp to <4 x int> ; <<4 x int>> [#uses=1] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=1] + %tmp2 = cast <8 x short> %tmp2 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp3 = call <4 x int> %llvm.ppc.altivec.vperm( <4 x int> %tmp, <4 x int> %tmp2, <16 x sbyte> < sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14, sbyte 14 > ) ; <<4 x int>> [#uses=1] + %tmp3 = cast <4 x int> %tmp3 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp3, <8 x short>* %A + ret void +} + +declare <4 x int> %llvm.ppc.altivec.vperm(<4 x int>, <4 x int>, <16 x sbyte>) + + +void %tb_l(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=8] + %tmp2 = load <16 x sbyte>* %B ; <<16 x sbyte>> [#uses=8] + %tmp = extractelement <16 x sbyte> %tmp, uint 8 ; <sbyte> [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp2, uint 8 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 9 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp2, uint 9 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 10 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp2, uint 10 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp2, uint 11 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 12 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp2, uint 12 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 13 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 13 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 14 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 14 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 15 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 15 ; <sbyte> [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %th_l(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=4] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=4] + %tmp = extractelement <8 x short> %tmp, uint 4 ; <short> [#uses=1] + %tmp3 = extractelement <8 x short> %tmp2, uint 4 ; <short> [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 5 ; <short> [#uses=1] + %tmp5 = extractelement <8 x short> %tmp2, uint 5 ; <short> [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 6 ; <short> [#uses=1] + %tmp7 = extractelement <8 x short> %tmp2, uint 6 ; <short> [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 7 ; <short> [#uses=1] + %tmp9 = extractelement <8 x short> %tmp2, uint 7 ; <short> [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %tw_l(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] + %tmp = extractelement <4 x int> %tmp, uint 2 ; <int> [#uses=1] + %tmp3 = extractelement <4 x int> %tmp2, uint 2 ; <int> [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 3 ; <int> [#uses=1] + %tmp5 = extractelement <4 x int> %tmp2, uint 3 ; <int> [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %tb_h(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=8] + %tmp2 = load <16 x sbyte>* %B ; <<16 x sbyte>> [#uses=8] + %tmp = extractelement <16 x sbyte> %tmp, uint 0 ; <sbyte> [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp2, uint 0 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 1 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp2, uint 1 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 2 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp2, uint 2 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 3 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp2, uint 3 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 4 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp2, uint 4 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 5 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp2, uint 5 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 6 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp2, uint 6 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 7 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp2, uint 7 ; <sbyte> [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %th_h(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=4] + %tmp2 = load <8 x short>* %B ; <<8 x short>> [#uses=4] + %tmp = extractelement <8 x short> %tmp, uint 0 ; <short> [#uses=1] + %tmp3 = extractelement <8 x short> %tmp2, uint 0 ; <short> [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 1 ; <short> [#uses=1] + %tmp5 = extractelement <8 x short> %tmp2, uint 1 ; <short> [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 2 ; <short> [#uses=1] + %tmp7 = extractelement <8 x short> %tmp2, uint 2 ; <short> [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 3 ; <short> [#uses=1] + %tmp9 = extractelement <8 x short> %tmp2, uint 3 ; <short> [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %tw_h(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] + %tmp = extractelement <4 x int> %tmp2, uint 0 ; <int> [#uses=1] + %tmp3 = extractelement <4 x int> %tmp, uint 0 ; <int> [#uses=1] + %tmp4 = extractelement <4 x int> %tmp2, uint 1 ; <int> [#uses=1] + %tmp5 = extractelement <4 x int> %tmp, uint 1 ; <int> [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %tw_h_flop(<4 x int>* %A, <4 x int>* %B) { + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp2 = load <4 x int>* %B ; <<4 x int>> [#uses=2] + %tmp = extractelement <4 x int> %tmp, uint 0 ; <int> [#uses=1] + %tmp3 = extractelement <4 x int> %tmp2, uint 0 ; <int> [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 1 ; <int> [#uses=1] + %tmp5 = extractelement <4 x int> %tmp2, uint 1 ; <int> [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + + +void %VMRG_UNARY_tb_l(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=16] + %tmp = extractelement <16 x sbyte> %tmp, uint 8 ; <sbyte> [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 8 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 9 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 9 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 10 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 10 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 11 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 12 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 12 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 13 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp, uint 13 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 14 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp, uint 14 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 15 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp, uint 15 ; <sbyte> [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %VMRG_UNARY_th_l(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=8] + %tmp = extractelement <8 x short> %tmp, uint 4 ; <short> [#uses=1] + %tmp3 = extractelement <8 x short> %tmp, uint 4 ; <short> [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 5 ; <short> [#uses=1] + %tmp5 = extractelement <8 x short> %tmp, uint 5 ; <short> [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 6 ; <short> [#uses=1] + %tmp7 = extractelement <8 x short> %tmp, uint 6 ; <short> [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 7 ; <short> [#uses=1] + %tmp9 = extractelement <8 x short> %tmp, uint 7 ; <short> [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %VMRG_UNARY_tw_l(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=4] + %tmp = extractelement <4 x int> %tmp, uint 2 ; <int> [#uses=1] + %tmp3 = extractelement <4 x int> %tmp, uint 2 ; <int> [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 3 ; <int> [#uses=1] + %tmp5 = extractelement <4 x int> %tmp, uint 3 ; <int> [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %VMRG_UNARY_tb_h(<16 x sbyte>* %A, <16 x sbyte>* %B) { +entry: + %tmp = load <16 x sbyte>* %A ; <<16 x sbyte>> [#uses=16] + %tmp = extractelement <16 x sbyte> %tmp, uint 0 ; <sbyte> [#uses=1] + %tmp3 = extractelement <16 x sbyte> %tmp, uint 0 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 1 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 1 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 2 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 2 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 3 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 3 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 4 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp, uint 4 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp, uint 5 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp, uint 5 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp, uint 6 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp, uint 6 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp, uint 7 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp, uint 7 ; <sbyte> [#uses=1] + %tmp18 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp19 = insertelement <16 x sbyte> %tmp18, sbyte %tmp3, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 15 ; <<16 x sbyte>> [#uses=1] + store <16 x sbyte> %tmp33, <16 x sbyte>* %A + ret void +} + +void %VMRG_UNARY_th_h(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=8] + %tmp = extractelement <8 x short> %tmp, uint 0 ; <short> [#uses=1] + %tmp3 = extractelement <8 x short> %tmp, uint 0 ; <short> [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 1 ; <short> [#uses=1] + %tmp5 = extractelement <8 x short> %tmp, uint 1 ; <short> [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 2 ; <short> [#uses=1] + %tmp7 = extractelement <8 x short> %tmp, uint 2 ; <short> [#uses=1] + %tmp8 = extractelement <8 x short> %tmp, uint 3 ; <short> [#uses=1] + %tmp9 = extractelement <8 x short> %tmp, uint 3 ; <short> [#uses=1] + %tmp10 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp11 = insertelement <8 x short> %tmp10, short %tmp3, uint 1 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 2 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 3 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 4 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 5 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 6 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 7 ; <<8 x short>> [#uses=1] + store <8 x short> %tmp17, <8 x short>* %A + ret void +} + +void %VMRG_UNARY_tw_h(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=4] + %tmp = extractelement <4 x int> %tmp, uint 0 ; <int> [#uses=1] + %tmp3 = extractelement <4 x int> %tmp, uint 0 ; <int> [#uses=1] + %tmp4 = extractelement <4 x int> %tmp, uint 1 ; <int> [#uses=1] + %tmp5 = extractelement <4 x int> %tmp, uint 1 ; <int> [#uses=1] + %tmp6 = insertelement <4 x int> undef, int %tmp, uint 0 ; <<4 x int>> [#uses=1] + %tmp7 = insertelement <4 x int> %tmp6, int %tmp3, uint 1 ; <<4 x int>> [#uses=1] + %tmp8 = insertelement <4 x int> %tmp7, int %tmp4, uint 2 ; <<4 x int>> [#uses=1] + %tmp9 = insertelement <4 x int> %tmp8, int %tmp5, uint 3 ; <<4 x int>> [#uses=1] + store <4 x int> %tmp9, <4 x int>* %A + ret void +} + +void %VPCKUHUM_unary(<8 x short>* %A, <8 x short>* %B) { +entry: + %tmp = load <8 x short>* %A ; <<8 x short>> [#uses=2] + %tmp = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=8] + %tmp3 = cast <8 x short> %tmp to <16 x sbyte> ; <<16 x sbyte>> [#uses=8] + %tmp = extractelement <16 x sbyte> %tmp, uint 1 ; <sbyte> [#uses=1] + %tmp4 = extractelement <16 x sbyte> %tmp, uint 3 ; <sbyte> [#uses=1] + %tmp5 = extractelement <16 x sbyte> %tmp, uint 5 ; <sbyte> [#uses=1] + %tmp6 = extractelement <16 x sbyte> %tmp, uint 7 ; <sbyte> [#uses=1] + %tmp7 = extractelement <16 x sbyte> %tmp, uint 9 ; <sbyte> [#uses=1] + %tmp8 = extractelement <16 x sbyte> %tmp, uint 11 ; <sbyte> [#uses=1] + %tmp9 = extractelement <16 x sbyte> %tmp, uint 13 ; <sbyte> [#uses=1] + %tmp10 = extractelement <16 x sbyte> %tmp, uint 15 ; <sbyte> [#uses=1] + %tmp11 = extractelement <16 x sbyte> %tmp3, uint 1 ; <sbyte> [#uses=1] + %tmp12 = extractelement <16 x sbyte> %tmp3, uint 3 ; <sbyte> [#uses=1] + %tmp13 = extractelement <16 x sbyte> %tmp3, uint 5 ; <sbyte> [#uses=1] + %tmp14 = extractelement <16 x sbyte> %tmp3, uint 7 ; <sbyte> [#uses=1] + %tmp15 = extractelement <16 x sbyte> %tmp3, uint 9 ; <sbyte> [#uses=1] + %tmp16 = extractelement <16 x sbyte> %tmp3, uint 11 ; <sbyte> [#uses=1] + %tmp17 = extractelement <16 x sbyte> %tmp3, uint 13 ; <sbyte> [#uses=1] + %tmp18 = extractelement <16 x sbyte> %tmp3, uint 15 ; <sbyte> [#uses=1] + %tmp19 = insertelement <16 x sbyte> undef, sbyte %tmp, uint 0 ; <<16 x sbyte>> [#uses=1] + %tmp20 = insertelement <16 x sbyte> %tmp19, sbyte %tmp4, uint 1 ; <<16 x sbyte>> [#uses=1] + %tmp21 = insertelement <16 x sbyte> %tmp20, sbyte %tmp5, uint 2 ; <<16 x sbyte>> [#uses=1] + %tmp22 = insertelement <16 x sbyte> %tmp21, sbyte %tmp6, uint 3 ; <<16 x sbyte>> [#uses=1] + %tmp23 = insertelement <16 x sbyte> %tmp22, sbyte %tmp7, uint 4 ; <<16 x sbyte>> [#uses=1] + %tmp24 = insertelement <16 x sbyte> %tmp23, sbyte %tmp8, uint 5 ; <<16 x sbyte>> [#uses=1] + %tmp25 = insertelement <16 x sbyte> %tmp24, sbyte %tmp9, uint 6 ; <<16 x sbyte>> [#uses=1] + %tmp26 = insertelement <16 x sbyte> %tmp25, sbyte %tmp10, uint 7 ; <<16 x sbyte>> [#uses=1] + %tmp27 = insertelement <16 x sbyte> %tmp26, sbyte %tmp11, uint 8 ; <<16 x sbyte>> [#uses=1] + %tmp28 = insertelement <16 x sbyte> %tmp27, sbyte %tmp12, uint 9 ; <<16 x sbyte>> [#uses=1] + %tmp29 = insertelement <16 x sbyte> %tmp28, sbyte %tmp13, uint 10 ; <<16 x sbyte>> [#uses=1] + %tmp30 = insertelement <16 x sbyte> %tmp29, sbyte %tmp14, uint 11 ; <<16 x sbyte>> [#uses=1] + %tmp31 = insertelement <16 x sbyte> %tmp30, sbyte %tmp15, uint 12 ; <<16 x sbyte>> [#uses=1] + %tmp32 = insertelement <16 x sbyte> %tmp31, sbyte %tmp16, uint 13 ; <<16 x sbyte>> [#uses=1] + %tmp33 = insertelement <16 x sbyte> %tmp32, sbyte %tmp17, uint 14 ; <<16 x sbyte>> [#uses=1] + %tmp34 = insertelement <16 x sbyte> %tmp33, sbyte %tmp18, uint 15 ; <<16 x sbyte>> [#uses=1] + %tmp34 = cast <16 x sbyte> %tmp34 to <8 x short> ; <<8 x short>> [#uses=1] + store <8 x short> %tmp34, <8 x short>* %A + ret void +} + +void %VPCKUWUM_unary(<4 x int>* %A, <4 x int>* %B) { +entry: + %tmp = load <4 x int>* %A ; <<4 x int>> [#uses=2] + %tmp = cast <4 x int> %tmp to <8 x short> ; <<8 x short>> [#uses=4] + %tmp3 = cast <4 x int> %tmp to <8 x short> ; <<8 x short>> [#uses=4] + %tmp = extractelement <8 x short> %tmp, uint 1 ; <short> [#uses=1] + %tmp4 = extractelement <8 x short> %tmp, uint 3 ; <short> [#uses=1] + %tmp5 = extractelement <8 x short> %tmp, uint 5 ; <short> [#uses=1] + %tmp6 = extractelement <8 x short> %tmp, uint 7 ; <short> [#uses=1] + %tmp7 = extractelement <8 x short> %tmp3, uint 1 ; <short> [#uses=1] + %tmp8 = extractelement <8 x short> %tmp3, uint 3 ; <short> [#uses=1] + %tmp9 = extractelement <8 x short> %tmp3, uint 5 ; <short> [#uses=1] + %tmp10 = extractelement <8 x short> %tmp3, uint 7 ; <short> [#uses=1] + %tmp11 = insertelement <8 x short> undef, short %tmp, uint 0 ; <<8 x short>> [#uses=1] + %tmp12 = insertelement <8 x short> %tmp11, short %tmp4, uint 1 ; <<8 x short>> [#uses=1] + %tmp13 = insertelement <8 x short> %tmp12, short %tmp5, uint 2 ; <<8 x short>> [#uses=1] + %tmp14 = insertelement <8 x short> %tmp13, short %tmp6, uint 3 ; <<8 x short>> [#uses=1] + %tmp15 = insertelement <8 x short> %tmp14, short %tmp7, uint 4 ; <<8 x short>> [#uses=1] + %tmp16 = insertelement <8 x short> %tmp15, short %tmp8, uint 5 ; <<8 x short>> [#uses=1] + %tmp17 = insertelement <8 x short> %tmp16, short %tmp9, uint 6 ; <<8 x short>> [#uses=1] + %tmp18 = insertelement <8 x short> %tmp17, short %tmp10, uint 7 ; <<8 x short>> [#uses=1] + %tmp18 = cast <8 x short> %tmp18 to <4 x int> ; <<4 x int>> [#uses=1] + store <4 x int> %tmp18, <4 x int>* %A + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/vec_spat.ll b/llvm/test/CodeGen/PowerPC/vec_spat.ll new file mode 100644 index 00000000000..6691995357b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_spat.ll @@ -0,0 +1,71 @@ +; Test that vectors are scalarized/lowered correctly. +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vspltw | wc -l | grep 2 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g3 | grep stfs | wc -l | grep 4 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vsplti | wc -l | grep 3 && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vsplth | wc -l | grep 1 + +%f4 = type <4 x float> +%i4 = type <4 x int> + +implementation + +void %splat(%f4* %P, %f4* %Q, float %X) { + %tmp = insertelement %f4 undef, float %X, uint 0 + %tmp2 = insertelement %f4 %tmp, float %X, uint 1 + %tmp4 = insertelement %f4 %tmp2, float %X, uint 2 + %tmp6 = insertelement %f4 %tmp4, float %X, uint 3 + %q = load %f4* %Q + %R = add %f4 %q, %tmp6 + store %f4 %R, %f4* %P + ret void +} + +void %splat_i4(%i4* %P, %i4* %Q, int %X) { + %tmp = insertelement %i4 undef, int %X, uint 0 + %tmp2 = insertelement %i4 %tmp, int %X, uint 1 + %tmp4 = insertelement %i4 %tmp2, int %X, uint 2 + %tmp6 = insertelement %i4 %tmp4, int %X, uint 3 + %q = load %i4* %Q + %R = add %i4 %q, %tmp6 + store %i4 %R, %i4* %P + ret void +} + +void %splat_imm_i32(%i4* %P, %i4* %Q, int %X) { + %q = load %i4* %Q + %R = add %i4 %q, <int -1, int -1, int -1, int -1> + store %i4 %R, %i4* %P + ret void +} + +void %splat_imm_i16(%i4* %P, %i4* %Q, int %X) { + %q = load %i4* %Q + %R = add %i4 %q, <int 65537, int 65537, int 65537, int 65537> + store %i4 %R, %i4* %P + ret void +} + +void %splat_h(short %tmp, <16 x ubyte>* %dst) { + %tmp = insertelement <8 x short> undef, short %tmp, uint 0 + %tmp72 = insertelement <8 x short> %tmp, short %tmp, uint 1 + %tmp73 = insertelement <8 x short> %tmp72, short %tmp, uint 2 + %tmp74 = insertelement <8 x short> %tmp73, short %tmp, uint 3 + %tmp75 = insertelement <8 x short> %tmp74, short %tmp, uint 4 + %tmp76 = insertelement <8 x short> %tmp75, short %tmp, uint 5 + %tmp77 = insertelement <8 x short> %tmp76, short %tmp, uint 6 + %tmp78 = insertelement <8 x short> %tmp77, short %tmp, uint 7 + %tmp78 = cast <8 x short> %tmp78 to <16 x ubyte> + store <16 x ubyte> %tmp78, <16 x ubyte>* %dst + ret void +} + +void %spltish(<16 x ubyte>* %A, <16 x ubyte>* %B) { + ; Gets converted to 16 x ubyte + %tmp = load <16 x ubyte>* %B + %tmp.s = cast <16 x ubyte> %tmp to <16 x sbyte> + %tmp4 = sub <16 x sbyte> %tmp.s, cast (<8 x short> < short 15, short 15, short 15, short 15, short 15, short 15, short 15, short 15 > to <16 x sbyte>) + %tmp4.u = cast <16 x sbyte> %tmp4 to <16 x ubyte> + store <16 x ubyte> %tmp4.u, <16 x ubyte>* %A + ret void +} + diff --git a/llvm/test/CodeGen/PowerPC/vec_vrsave.ll b/llvm/test/CodeGen/PowerPC/vec_vrsave.ll new file mode 100644 index 00000000000..936580aa798 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_vrsave.ll @@ -0,0 +1,13 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vrlw && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep spr && +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vrsave + +<4 x int> %test_rol() { + ret <4 x int> < int -11534337, int -11534337, int -11534337, int -11534337 > +} + +<4 x int> %test_arg(<4 x int> %A, <4 x int> %B) { + %C = add <4 x int> %A, %B + ret <4 x int> %C +} + diff --git a/llvm/test/CodeGen/PowerPC/vec_zero.ll b/llvm/test/CodeGen/PowerPC/vec_zero.ll new file mode 100644 index 00000000000..c845c0e8db2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vec_zero.ll @@ -0,0 +1,8 @@ +; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | grep vxor + +void %foo(<4 x float> *%P) { + %T = load <4 x float> * %P + %S = add <4 x float> zeroinitializer, %T + store <4 x float> %S, <4 x float>* %P + ret void +} |
