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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2017-01-26 15:02:31 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2017-01-26 15:02:31 +0000 |
| commit | 82149a1aa961a7870c2cb8f6bad6fb4f1dc9a29a (patch) | |
| tree | 23bdf08183d90600f7d6d8547b50c1fa6992cd92 /llvm/test/CodeGen/PowerPC | |
| parent | a98b5fd999bda84b6585875a92d5f31da2b371af (diff) | |
| download | bcm5719-llvm-82149a1aa961a7870c2cb8f6bad6fb4f1dc9a29a.tar.gz bcm5719-llvm-82149a1aa961a7870c2cb8f6bad6fb4f1dc9a29a.zip | |
Use shouldAssumeDSOLocal in classifyGlobalReference.
And teach shouldAssumeDSOLocal that ppc has no copy relocations.
The resulting code handle a few more case than before. For example, it
knows that a weak symbol can be resolved to another .o file, but it
will still be in the main executable.
llvm-svn: 293180
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/mcm-obj.ll | 5 |
2 files changed, 3 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll index 1990f6b51d5..5317829c6ce 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll @@ -196,7 +196,7 @@ define void @t17(i64 %v) nounwind { %1 = add nsw i64 %v, 1 store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8 ; ELF64: addis -; ELF64: ld +; ELF64: addi ; ELF64: addi ; ELF64: lis ; ELF64: ori diff --git a/llvm/test/CodeGen/PowerPC/mcm-obj.ll b/llvm/test/CodeGen/PowerPC/mcm-obj.ll index 6b5b0c2b742..fa899b5b301 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-obj.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-obj.ll @@ -108,11 +108,10 @@ entry: ret i32 %0 } -; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for -; accessing tentatively declared variable ti. +; Verify generation of relocations foraccessing variable ti. ; ; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]] -; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM6]] ; ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]] ; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]] |
