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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2018-02-01 21:09:04 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2018-02-01 21:09:04 +0000 |
| commit | 77e34f15c93e2445708839990a1289daecdc5141 (patch) | |
| tree | c9e28c2fd2ab7f99a994fb48aa7be539573ef853 /llvm/test/CodeGen/PowerPC | |
| parent | 47ff8f457f821f2144b998a2c4e287f4c7bb0d37 (diff) | |
| download | bcm5719-llvm-77e34f15c93e2445708839990a1289daecdc5141.tar.gz bcm5719-llvm-77e34f15c93e2445708839990a1289daecdc5141.zip | |
[PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitive
This is a rather non-controversial change. We were missing these instructions
from the list of instructions that are lane-sensitive. These two put the result
into lane 0 (BE) or 3 (LE) regardless of the input. This patch fixes PR36068.
llvm-svn: 324005
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr36068.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/pr36068.ll b/llvm/test/CodeGen/PowerPC/pr36068.ll new file mode 100644 index 00000000000..aac659bfb70 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr36068.ll @@ -0,0 +1,18 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \ +; RUN: FileCheck %s + +@glob = common local_unnamed_addr global <4 x float> zeroinitializer, align 4 + +; Function Attrs: norecurse nounwind +define void @test(float %a, <4 x float>* nocapture readonly %b) { +; CHECK-LABEL: test +; CHECK: xscvdpspn [[REG:[0-9]+]], 1 +; CHECK: xxspltw {{[0-9]+}}, [[REG]], 0 +entry: + %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0 + %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer + %0 = load <4 x float>, <4 x float>* %b, align 4 + %mul = fmul <4 x float> %splat.splat, %0 + store <4 x float> %mul, <4 x float>* @glob, align 4 + ret void +} |
