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| author | Hal Finkel <hfinkel@anl.gov> | 2012-08-04 14:10:46 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-08-04 14:10:46 +0000 |
| commit | 70381a7b1877e17eddf2ef80122005a8ac02d783 (patch) | |
| tree | d557d26e04c24c3c61f61142ec985b9153a2a2c3 /llvm/test/CodeGen/PowerPC | |
| parent | ef731edf530059ed8a1324043b5934ee4f59aa70 (diff) | |
| download | bcm5719-llvm-70381a7b1877e17eddf2ef80122005a8ac02d783.tar.gz bcm5719-llvm-70381a7b1877e17eddf2ef80122005a8ac02d783.zip | |
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
llvm-svn: 161302
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll b/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll new file mode 100644 index 00000000000..c1df3c7ec21 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ppc64-cyclecounter.ll @@ -0,0 +1,15 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" +; RUN: llc < %s | FileCheck %s + +define i64 @test1() nounwind { +entry: + %r = call i64 @llvm.readcyclecounter() + ret i64 %r +} + +; CHECK: @test1 +; CHECK: mftb + +declare i64 @llvm.readcyclecounter() + |
