Do full codegen for various tests. NFC

llvm-svn: 296305

2 files changed, 65 insertions, 44 deletions

diff --git a/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
index 264967157d7..56f4a4173ef 100644
--- a/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
@@ -1,17 +1,33 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin | grep extsw | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
 
 @lens = external global i8*             ; <i8**> [#uses=1]
 @vals = external global i32*            ; <i32**> [#uses=1]
 
 define i32 @test(i32 %i) {
-        %tmp = load i8*, i8** @lens          ; <i8*> [#uses=1]
-        %tmp1 = getelementptr i8, i8* %tmp, i32 %i          ; <i8*> [#uses=1]
-        %tmp.upgrd.1 = load i8, i8* %tmp1           ; <i8> [#uses=1]
-        %tmp2 = zext i8 %tmp.upgrd.1 to i32             ; <i32> [#uses=1]
-        %tmp3 = load i32*, i32** @vals                ; <i32*> [#uses=1]
-        %tmp5 = sub i32 1, %tmp2                ; <i32> [#uses=1]
-        %tmp6 = getelementptr i32, i32* %tmp3, i32 %tmp5             ; <i32*> [#uses=1]
-        %tmp7 = load i32, i32* %tmp6         ; <i32> [#uses=1]
-        ret i32 %tmp7
+; CHECK-LABEL: test:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    addis 4, 2, .LC0@toc@ha
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    addis 5, 2, .LC1@toc@ha
+; CHECK-NEXT:    ld 4, .LC0@toc@l(4)
+; CHECK-NEXT:    ld 4, 0(4)
+; CHECK-NEXT:    lbzx 3, 4, 3
+; CHECK-NEXT:    ld 4, .LC1@toc@l(5)
+; CHECK-NEXT:    subfic 3, 3, 1
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    ld 4, 0(4)
+; CHECK-NEXT:    sldi 3, 3, 2
+; CHECK-NEXT:    lwzx 3, 4, 3
+; CHECK-NEXT:    blr
+  %tmp = load i8*, i8** @lens          ; <i8*> [#uses=1]
+  %tmp1 = getelementptr i8, i8* %tmp, i32 %i          ; <i8*> [#uses=1]
+  %tmp.upgrd.1 = load i8, i8* %tmp1           ; <i8> [#uses=1]
+  %tmp2 = zext i8 %tmp.upgrd.1 to i32             ; <i32> [#uses=1]
+  %tmp3 = load i32*, i32** @vals                ; <i32*> [#uses=1]
+  %tmp5 = sub i32 1, %tmp2                ; <i32> [#uses=1]
+  %tmp6 = getelementptr i32, i32* %tmp3, i32 %tmp5             ; <i32*> [#uses=1]
+  %tmp7 = load i32, i32* %tmp6         ; <i32> [#uses=1]
+  ret i32 %tmp7
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
index 335bb403cd7..752ebe0c9d8 100644
--- a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN: -mcpu=pwr8 < %s | FileCheck %s
 
@@ -6,6 +7,15 @@
 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    lwz 4, 0(4)
+; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
+; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    sub 3, 3, 4
+; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
   %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
@@ -15,18 +25,20 @@ entry:
   %and.i4 = and i32 %1, 8
   %cmp.i5 = icmp ult i32 %and.i, %and.i4
   ret i1 %cmp.i5
-
-; CHECK-LABEL: @test1
-; CHECK: rlwinm [[REG1:[0-9]*]]
-; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
-; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG1]], [[REG2]]
-; CHECK-NEXT: rldicl 3, [[REG3]]
-; CHECK: blr
-
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    lwz 4, 0(4)
+; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
+; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    sub 3, 4, 3
+; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
   %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
@@ -36,19 +48,19 @@ entry:
   %and.i4 = and i32 %1, 8
   %cmp.i5 = icmp ule i32 %and.i, %and.i4
   ret i1 %cmp.i5
-
-; CHECK-LABEL: @test2
-; CHECK: rlwinm [[REG1:[0-9]*]]
-; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
-; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG2]], [[REG1]]
-; CHECK-NEXT: rldicl [[REG4:[0-9]*]], [[REG3]]
-; CHECK-NEXT: xori 3, [[REG4]], 1
-; CHECK: blr
-
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    lwz 4, 0(4)
+; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
+; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    sub 3, 4, 3
+; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
   %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
@@ -58,18 +70,20 @@ entry:
   %and.i4 = and i32 %1, 8
   %cmp.i5 = icmp ugt i32 %and.i, %and.i4
   ret i1 %cmp.i5
-
-; CHECK-LABEL: @test3
-; CHECK: rlwinm [[REG1:[0-9]*]]
-; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
-; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG2]], [[REG1]]
-; CHECK-NEXT: rldicl 3, [[REG3]]
-; CHECK: blr
-
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    lwz 4, 0(4)
+; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
+; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
+; CHECK-NEXT:    sub 3, 3, 4
+; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
   %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
@@ -79,15 +93,6 @@ entry:
   %and.i4 = and i32 %1, 8
   %cmp.i5 = icmp uge i32 %and.i, %and.i4
   ret i1 %cmp.i5
-
-; CHECK-LABEL: @test4
-; CHECK: rlwinm [[REG1:[0-9]*]]
-; CHECK-NEXT: rlwinm [[REG2:[0-9]*]]
-; CHECK-NEXT: sub [[REG3:[0-9]*]], [[REG1]], [[REG2]]
-; CHECK-NEXT: rldicl [[REG4:[0-9]*]], [[REG3]]
-; CHECK-NEXT: xori 3, [[REG4]], 1
-; CHECK: blr
-
 }
 
 !1 = !{!2, !2, i64 0}