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authorBenjamin Kramer <benny.kra@googlemail.com>2013-01-12 19:06:44 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2013-01-12 19:06:44 +0000
commit5ea0349ef59288bb239036b87bbcfcb41e3f62e8 (patch)
treee0fa1d59cd695d6756e395dba163f62a1e888d56 /llvm/test/CodeGen/PowerPC
parent3128a11ee88a78429d8449fc4d517516960316bc (diff)
downloadbcm5719-llvm-5ea0349ef59288bb239036b87bbcfcb41e3f62e8.tar.gz
bcm5719-llvm-5ea0349ef59288bb239036b87bbcfcb41e3f62e8.zip
When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. llvm-svn: 172322
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
-rw-r--r--llvm/test/CodeGen/PowerPC/vec_extload.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vec_extload.ll b/llvm/test/CodeGen/PowerPC/vec_extload.ll
index 42334d7030d..998645d90da 100644
--- a/llvm/test/CodeGen/PowerPC/vec_extload.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extload.ll
@@ -15,7 +15,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
ret <16 x i8> %c
}
; CHECK: v16si8_sext_in_reg:
-; CHECK: vsrb
+; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
@@ -37,7 +37,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
ret <8 x i16> %c
}
; CHECK: v8si16_sext_in_reg:
-; CHECK: vsrh
+; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
@@ -61,7 +61,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
ret <4 x i32> %c
}
; CHECK: v4si32_sext_in_reg:
-; CHECK: vsrw
+; CHECK: vslw
; CHECK: vsraw
; CHECK: blr
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