revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)

This change is exposing UB in source code - as was warned/predicted. :)
See D44909 for discussion. Reverting while we figure out how to fix things.

llvm-svn: 329920

4 files changed, 48 insertions, 13 deletions

diff --git a/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll b/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
index 4a36f2404b6..eff0c28e0f5 100644
--- a/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll
@@ -5,7 +5,18 @@
 define float @f_i128_f(float %v) {
 ; CHECK-LABEL: f_i128_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    friz 1, 1
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    bl __fixsfti
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    bl __floattisf
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %a = fptosi float %v to i128
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
index 942bdf5e028..be55d4ab853 100644
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -11,7 +11,8 @@ entry:
   ret float %conv1
 
 ; FPCVT-LABEL: @fool
-; FPCVT: friz 1, 1
+; FPCVT: fctidz [[REG1:[0-9]+]], 1
+; FPCVT: fcfids 1, [[REG1]]
 ; FPCVT: blr
 
 ; PPC64-LABEL: @fool
@@ -29,7 +30,8 @@ entry:
   ret double %conv1
 
 ; FPCVT-LABEL: @foodl
-; FPCVT: friz 1, 1
+; FPCVT: fctidz [[REG1:[0-9]+]], 1
+; FPCVT: fcfid 1, [[REG1]]
 ; FPCVT: blr
 
 ; PPC64-LABEL: @foodl
@@ -46,7 +48,8 @@ entry:
   ret float %conv1
 
 ; FPCVT-LABEL: @fooul
-; FPCVT: friz 1, 1
+; FPCVT: fctiduz [[REG1:[0-9]+]], 1
+; FPCVT: fcfidus 1, [[REG1]]
 ; FPCVT: blr
 }
 
@@ -58,7 +61,8 @@ entry:
   ret double %conv1
 
 ; FPCVT-LABEL: @fooudl
-; FPCVT: friz 1, 1
+; FPCVT: fctiduz [[REG1:[0-9]+]], 1
+; FPCVT: fcfidu 1, [[REG1]]
 ; FPCVT: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
index ef529ed254e..99f21a117d5 100644
--- a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
+++ b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
@@ -4,7 +4,8 @@
 define <4 x float> @truncf32(<4 x float> %a) {
 ; CHECK-LABEL: truncf32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvrspiz 34, 34
+; CHECK-NEXT:    xvcvspsxws 0, 34
+; CHECK-NEXT:    xvcvsxwsp 34, 0
 ; CHECK-NEXT:    blr
   %t0 = fptosi <4 x float> %a to <4 x i32>
   %t1 = sitofp <4 x i32> %t0 to <4 x float>
@@ -14,7 +15,8 @@ define <4 x float> @truncf32(<4 x float> %a) {
 define <2 x double> @truncf64(<2 x double> %a) {
 ; CHECK-LABEL: truncf64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvrdpiz 34, 34
+; CHECK-NEXT:    xvcvdpsxds 34, 34
+; CHECK-NEXT:    xvcvsxddp 34, 34
 ; CHECK-NEXT:    blr
   %t0 = fptosi <2 x double> %a to <2 x i64>
   %t1 = sitofp <2 x i64> %t0 to <2 x double>
@@ -24,7 +26,8 @@ define <2 x double> @truncf64(<2 x double> %a) {
 define <4 x float> @truncf32u(<4 x float> %a) {
 ; CHECK-LABEL: truncf32u:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvrspiz 34, 34
+; CHECK-NEXT:    xvcvspuxws 0, 34
+; CHECK-NEXT:    xvcvuxwsp 34, 0
 ; CHECK-NEXT:    blr
   %t0 = fptoui <4 x float> %a to <4 x i32>
   %t1 = uitofp <4 x i32> %t0 to <4 x float>
@@ -34,7 +37,8 @@ define <4 x float> @truncf32u(<4 x float> %a) {
 define <2 x double> @truncf64u(<2 x double> %a) {
 ; CHECK-LABEL: truncf64u:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xvrdpiz 34, 34
+; CHECK-NEXT:    xvcvdpuxds 34, 34
+; CHECK-NEXT:    xvcvuxddp 34, 34
 ; CHECK-NEXT:    blr
   %t0 = fptoui <2 x double> %a to <2 x i64>
   %t1 = uitofp <2 x i64> %t0 to <2 x double>
diff --git a/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll b/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
index 0bbaf3493fd..713adb4dfd0 100644
--- a/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll
@@ -36,7 +36,11 @@ entry:
   ret float %conv1
 
 ; CHECK-LABEL: @foo
-; CHECK: friz 1, 1
+; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
+; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
+; CHECK: stfiwx [[REG2]], 0, [[REG1]]
+; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
+; CHECK: fcfids 1, [[REG3]]
 ; CHECK: blr
 }
 
@@ -48,7 +52,11 @@ entry:
   ret double %conv1
 
 ; CHECK-LABEL: @food
-; CHECK: friz 1, 1
+; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
+; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
+; CHECK: stfiwx [[REG2]], 0, [[REG1]]
+; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
+; CHECK: fcfid 1, [[REG3]]
 ; CHECK: blr
 }
 
@@ -60,7 +68,11 @@ entry:
   ret float %conv1
 
 ; CHECK-LABEL: @foou
-; CHECK: friz 1, 1
+; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
+; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
+; CHECK: stfiwx [[REG2]], 0, [[REG1]]
+; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
+; CHECK: fcfidus 1, [[REG3]]
 ; CHECK: blr
 }
 
@@ -72,7 +84,11 @@ entry:
   ret double %conv1
 
 ; CHECK-LABEL: @fooud
-; CHECK: friz 1, 1
+; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
+; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
+; CHECK: stfiwx [[REG2]], 0, [[REG1]]
+; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
+; CHECK: fcfidu 1, [[REG3]]
 ; CHECK: blr
 }