diff options
| author | Jonathan Roelofs <jonathan@codesourcery.com> | 2015-08-10 19:01:27 +0000 |
|---|---|---|
| committer | Jonathan Roelofs <jonathan@codesourcery.com> | 2015-08-10 19:01:27 +0000 |
| commit | 49e46ce8e2fbf7952d46aaee1955a0e00b15d175 (patch) | |
| tree | 8612d68e097c120d240686eb052990deac86848c /llvm/test/CodeGen/PowerPC | |
| parent | fc2b6fa31c11989e4a9ec41d785d9f92e5766d93 (diff) | |
| download | bcm5719-llvm-49e46ce8e2fbf7952d46aaee1955a0e00b15d175.tar.gz bcm5719-llvm-49e46ce8e2fbf7952d46aaee1955a0e00b15d175.zip | |
Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI
I looked into adding a warning / error for this to FileCheck, but there doesn't
seem to be a good way to avoid it triggering on the instances of it in RUN lines.
llvm-svn: 244481
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/rm-zext.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/sdiv-pow2.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll | 6 |
4 files changed, 11 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll index ad8ed38da7f..028006320cb 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll @@ -10,7 +10,7 @@ define void @main() { } ; CHECK-LABEL: @main -; CHECK-DAG li 4, 0 +; CHECK-DAG: li 4, 0 ; CHECK-DAG: crxor 6, 6, 6 ; CHECK: bl printf diff --git a/llvm/test/CodeGen/PowerPC/rm-zext.ll b/llvm/test/CodeGen/PowerPC/rm-zext.ll index 97c546c0145..df5fe4f7a15 100644 --- a/llvm/test/CodeGen/PowerPC/rm-zext.ll +++ b/llvm/test/CodeGen/PowerPC/rm-zext.ll @@ -9,7 +9,7 @@ entry: %shr2 = lshr i32 %mul, 5 ret i32 %shr2 -; CHECK-LABEL @foo +; CHECK-LABEL: @foo ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } @@ -23,7 +23,7 @@ entry: %or = or i32 %shr, %shl ret i32 %or -; CHECK-LABEL @test6 +; CHECK-LABEL: @test6 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } @@ -34,7 +34,7 @@ entry: %cond = select i1 %cmp, i32 %a, i32 %b ret i32 %cond -; CHECK-LABEL @min +; CHECK-LABEL: @min ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } diff --git a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll index 5ec019dfb4a..d1f60da6c74 100644 --- a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll +++ b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll @@ -9,7 +9,7 @@ entry: %div = sdiv i32 %a, 8 ret i32 %div -; CHECK-LABEL @foo4 +; CHECK-LABEL: @foo4 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]] ; CHECK: extsw 3, [[REG2]] @@ -22,12 +22,12 @@ entry: %div = sdiv i64 %a, 8 ret i64 %div -; CHECK-LABEL @foo8 +; CHECK-LABEL: @foo8 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze 3, [[REG1]] ; CHECK: blr -; CHECK-32-LABEL @foo8 +; CHECK-32-LABEL: @foo8 ; CHECK-32-NOT: sradi ; CHECK-32: blr } @@ -58,7 +58,7 @@ entry: ; CHECK: neg 3, [[REG2]] ; CHECK: blr -; CHECK-32-LABEL @foo8n +; CHECK-32-LABEL: @foo8n ; CHECK-32-NOT: sradi ; CHECK-32: blr } diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll index f7ebf479755..9e79b52c404 100644 --- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -14,7 +14,7 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind { %result = add <1 x i128> %x, <i128 1> ret <1 x i128> %result ; CHECK-LABEL: @increment_by_one -; CHECK vadduqm 2, 2, 3 +; CHECK: vadduqm 2, 2, 3 } define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind { @@ -37,7 +37,7 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind { %result = sub <1 x i128> %x, <i128 1> ret <1 x i128> %result ; CHECK-LABEL: @decrement_by_one -; CHECK vsubuqm 2, 2, 3 +; CHECK: vsubuqm 2, 2, 3 } define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { @@ -46,7 +46,7 @@ define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { %result = sub <1 x i128> %x, %tmpvec2 ret <1 x i128> %result ; CHECK-LABEL: @decrement_by_val -; CHECK vsubuqm 2, 2, 3 +; CHECK: vsubuqm 2, 2, 3 } declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, |

