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| author | Sanjay Patel <spatel@rotateright.com> | 2019-12-13 09:40:33 -0500 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-12-13 14:03:54 -0500 |
| commit | 2f0c7fd2dbd06ae5f25b0c72b2b8f2a1c5baeb72 (patch) | |
| tree | 05694975281fbc7378ff5b8849ef90a8cd0db81d /llvm/test/CodeGen/PowerPC | |
| parent | ed50e6060b1c51ec4a5dad6c01a64a5f1526cdb5 (diff) | |
| download | bcm5719-llvm-2f0c7fd2dbd06ae5f25b0c72b2b8f2a1c5baeb72.tar.gz bcm5719-llvm-2f0c7fd2dbd06ae5f25b0c72b2b8f2a1c5baeb72.zip | |
[DAGCombiner] fold shift-trunc-shift to shift-mask-trunc (2nd try)
The initial attempt (rG89633320) botched the logic by reversing
the source/dest types. Added x86 tests for additional coverage.
The vector tests show a potential improvement (fold vector load
instead of broadcasting), but that's a known/existing problem.
This fold is done in IR by instcombine, and we have a special
form of it already here in DAGCombiner, but we want the more
general transform too:
https://rise4fun.com/Alive/3jZm
Name: general
Pre: (C1 + zext(C2) < 64)
%s = lshr i64 %x, C1
%t = trunc i64 %s to i16
%r = lshr i16 %t, C2
=>
%s2 = lshr i64 %x, C1 + zext(C2)
%a = and i64 %s2, zext((1 << (16 - C2)) - 1)
%r = trunc %a to i16
Name: special
Pre: C1 == 48
%s = lshr i64 %x, C1
%t = trunc i64 %s to i16
%r = lshr i16 %t, C2
=>
%s2 = lshr i64 %x, C1 + zext(C2)
%r = trunc %s2 to i16
...because D58017 exposes a regression without this fold.
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/trunc-srl-load.ll | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll index a1af256eccb..5dc0534ef44 100644 --- a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll +++ b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll @@ -25,8 +25,7 @@ cond.false: ; preds = %entry define i32 @sh_trunc_sh(i64 %x) { ; CHECK-LABEL: sh_trunc_sh: ; CHECK: # %bb.0: -; CHECK-NEXT: rldicl 3, 3, 51, 13 -; CHECK-NEXT: srwi 3, 3, 4 +; CHECK-NEXT: rldicl 3, 3, 47, 36 ; CHECK-NEXT: blr %s = lshr i64 %x, 13 %t = trunc i64 %s to i32 |
