[DAGCombine] Improve ReduceLoad for SRL

Recommitting r329283, third time lucky...

If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.

Differential Revision: https://reviews.llvm.org/D41350

llvm-svn: 329551

1 files changed, 18 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
new file mode 100644
index 00000000000..4cb557f031a
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
+
+; CHECK-LABEL: trunc_srl_load
+; CHECK-NOT: lhz 4, 4(0)
+; CHECK: lhz 4, 2(0)
+define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
+entry:
+  %bf.load.i = load i64, i64* null, align 8
+  %bf.lshr.i = lshr i64 %bf.load.i, 32
+  %0 = trunc i64 %bf.lshr.i to i32
+  %bf.cast.i = and i32 %0, 65535
+  %cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo
+  br i1 %cmp.i, label %exit, label %cond.false
+exit:       ; preds = %entry
+  unreachable
+cond.false:                                       ; preds = %entry
+  unreachable
+}