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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-10 22:02:30 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-10 22:02:30 +0000 |
| commit | 0b382a7cb8b0a46fc69f94dd59d83855b72f1277 (patch) | |
| tree | a9d9a5170c5a070a7bc8c835e95676b3283b65e3 /llvm/test/CodeGen/PowerPC | |
| parent | 7acb42a41a7ed67f19553cd3617aacbca832a458 (diff) | |
| download | bcm5719-llvm-0b382a7cb8b0a46fc69f94dd59d83855b72f1277.tar.gz bcm5719-llvm-0b382a7cb8b0a46fc69f94dd59d83855b72f1277.zip | |
DAG: Avoid OOB when legalizing vector indexing
If a vector index is out of bounds, the result is supposed to be
undefined but is not undefined behavior. Change the legalization
for indexing the vector on the stack so that an out of bounds
index does not create an out of bounds memory access.
llvm-svn: 291604
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll index b61acab7f7c..98862cd049a 100644 --- a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll +++ b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll @@ -23,7 +23,7 @@ entry: ; CHECK: mfvsrd [[TOGPR:[0-9]+]], ; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]] ; CHECK: extsw 3, [[RSHREG]] -; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2 +; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 ; CHECK-P7-DAG: stxvw4x 34, ; CHECK-P7: lwax 3, [[ELEMOFFREG]], ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2 @@ -52,7 +52,7 @@ entry: ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] ; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] ; CHECK: mfvsrd 3, -; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 3 +; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 3, 28, 28 ; CHECK-P7-DAG: stxvd2x 34, ; CHECK-P7: ldx 3, [[ELEMOFFREG]], ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 @@ -75,7 +75,7 @@ entry: ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[TRUNCREG]] ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] ; CHECK: xscvspdpn 1, -; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2 +; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 ; CHECK-P7-DAG: stxvw4x 34, ; CHECK-P7: lfsx 1, [[ELEMOFFREG]], ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2 |
