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authorEli Friedman <eli.friedman@gmail.com>2011-12-09 01:16:26 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-12-09 01:16:26 +0000
commit053a724483dcb9707e06462018c352b9a4bda2af (patch)
treedf62815263f96a4452c8761978538918a19ea7db /llvm/test/CodeGen/PowerPC
parent329b351807a8964e03f2acb97265ca7d74abaeeb (diff)
downloadbcm5719-llvm-053a724483dcb9707e06462018c352b9a4bda2af.tar.gz
bcm5719-llvm-053a724483dcb9707e06462018c352b9a4bda2af.zip
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
llvm-svn: 146219
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
-rw-r--r--llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll16
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
new file mode 100644
index 00000000000..a18829e1bce
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s
+
+define void @test(i32* nocapture %x, i64* %xx, i32* %yp) nounwind uwtable ssp {
+entry:
+ %yy = load i32* %yp
+ %y = add i32 %yy, 1
+ %z = zext i32 %y to i64
+ %z2 = shl i64 %z, 32
+ store i64 %z2, i64* %xx, align 4
+ ret void
+
+; CHECK: test:
+; CHECK: sldi {{.*}}, {{.*}}, 32
+; Note: it's okay if someday CodeGen gets smart enough to optimize out
+; the shift.
+}
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