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| author | Lei Huang <lei@ca.ibm.com> | 2018-05-24 03:20:28 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-05-24 03:20:28 +0000 |
| commit | f4ec67822fb6dd96bb9959d84178d220833325c2 (patch) | |
| tree | 1b8534c9ab380c580259fb27d96731333dfe15e2 /llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll | |
| parent | 4d53b744ca0e8f7efa43da5b43ed42120a3b32d9 (diff) | |
| download | bcm5719-llvm-f4ec67822fb6dd96bb9959d84178d220833325c2.tar.gz bcm5719-llvm-f4ec67822fb6dd96bb9959d84178d220833325c2.zip | |
[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
The match pattern in the definition of LXSDX is xoaddr, so the Pseudo
instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post
RA based on the register pressure. To avoid ambiguity, we need to remove the
select pattern for LXSDX, same as what was done for LXSD. STXSDX also have
the same issue.
Patch by Qing Shan Zhang (steven.zhang).
Differential Revision: https://reviews.llvm.org/D47178
llvm-svn: 333150
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll index d8ea0dc992f..ec6646ddb69 100644 --- a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -123,7 +123,7 @@ entry: store volatile float %conv, float* %ff, align 4 ret void ; CHECK-LABEL: @dblToFloat -; CHECK: lxsdx [[REGLD5:[0-9]+]], +; CHECK: lfdx [[REGLD5:[0-9]+]], ; CHECK: stfsx [[REGLD5]], ; CHECK-P9-LABEL: @dblToFloat ; CHECK-P9: lfd [[REGLD5:[0-9]+]], @@ -140,7 +140,7 @@ entry: ret void ; CHECK-LABEL: @floatToDbl ; CHECK: lfsx [[REGLD5:[0-9]+]], -; CHECK: stxsdx [[REGLD5]], +; CHECK: stfdx [[REGLD5]], ; CHECK-P9-LABEL: @floatToDbl ; CHECK-P9: lfs [[REGLD5:[0-9]+]], ; CHECK-P9: stfd [[REGLD5]], |
