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| author | Tanya Lattner <tonic@nondot.org> | 2008-02-19 08:07:33 +0000 |
|---|---|---|
| committer | Tanya Lattner <tonic@nondot.org> | 2008-02-19 08:07:33 +0000 |
| commit | a99d8b5a9a2c8cabdbbb11eb2f0c885573560ee1 (patch) | |
| tree | f0113c0d6322f1a5e9b495352342e8eedd08e04d /llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll | |
| parent | a00c808d4050cece0dd328d614aa6d01b9824f8f (diff) | |
| download | bcm5719-llvm-a99d8b5a9a2c8cabdbbb11eb2f0c885573560ee1.tar.gz bcm5719-llvm-a99d8b5a9a2c8cabdbbb11eb2f0c885573560ee1.zip | |
Remove llvm-upgrade and update tests.
llvm-svn: 47325
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll | 48 |
1 files changed, 21 insertions, 27 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll index 6177b5f4c68..5bb1b608341 100644 --- a/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll @@ -1,42 +1,36 @@ -; RUN: llvm-upgrade < %s | llvm-as | llc -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm -<4 x float> %test_uu72(<4 x float> *%P1, <4 x float> *%P2) { - %V1 = load <4 x float> *%P1 - %V2 = load <4 x float> *%P2 - ; vmrglw + vsldoi - %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, - <4 x uint> <uint undef, uint undef, uint 7, uint 2> +define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1] ret <4 x float> %V3 } -<4 x float> %test_30u5(<4 x float> *%P1, <4 x float> *%P2) { - %V1 = load <4 x float> *%P1 - %V2 = load <4 x float> *%P2 - %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, - <4 x uint> <uint 3, uint 0, uint undef, uint 5> +define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 > ; <<4 x float>> [#uses=1] ret <4 x float> %V3 } -<4 x float> %test_3u73(<4 x float> *%P1, <4 x float> *%P2) { - %V1 = load <4 x float> *%P1 - %V2 = load <4 x float> *%P2 - %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, - <4 x uint> <uint 3, uint undef, uint 7, uint 3> +define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 > ; <<4 x float>> [#uses=1] ret <4 x float> %V3 } -<4 x float> %test_3774(<4 x float> *%P1, <4 x float> *%P2) { - %V1 = load <4 x float> *%P1 - %V2 = load <4 x float> *%P2 - %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, - <4 x uint> <uint 3, uint 7, uint 7, uint 4> +define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; <<4 x float>> [#uses=1] ret <4 x float> %V3 } -<4 x float> %test_4450(<4 x float> *%P1, <4 x float> *%P2) { - %V1 = load <4 x float> *%P1 - %V2 = load <4 x float> *%P2 - %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, - <4 x uint> <uint 4, uint 4, uint 5, uint 0> +define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; <<4 x float>> [#uses=1] ret <4 x float> %V3 } |
