[CodeGen] Unify MBB reference format in both MIR and debug output

As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665

1 files changed, 18 insertions, 18 deletions

diff --git a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
index b07c905ceec..7e397f54684 100644
--- a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
@@ -4,12 +4,12 @@
 
 define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test1:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test1:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 56
 ; CHECK-BE-NEXT:    blr
@@ -21,12 +21,12 @@ entry:
 
 define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test2:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test2:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    extsb 3, 3
 ; CHECK-BE-NEXT:    blr
@@ -38,13 +38,13 @@ entry:
 
 define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test3:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test3:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
@@ -57,13 +57,13 @@ entry:
 
 define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test4:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test4:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsh 3, 3
@@ -76,12 +76,12 @@ entry:
 
 define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test5:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test5:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
@@ -93,13 +93,13 @@ entry:
 
 define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test6:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test6:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsw 3, 3
@@ -113,13 +113,13 @@ entry:
 ; Test with immediate index
 define zeroext i8 @test7(<16 x i8> %a) {
 ; CHECK-LE-LABEL: test7:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 1
 ; CHECK-LE-NEXT:    vextubrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test7:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 1
 ; CHECK-BE-NEXT:    vextublx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 56
@@ -132,13 +132,13 @@ entry:
 
 define zeroext i16 @test8(<8 x i16> %a) {
 ; CHECK-LE-LABEL: test8:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 2
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test8:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 2
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
@@ -151,12 +151,12 @@ entry:
 
 define zeroext i32 @test9(<4 x i32> %a) {
 ; CHECK-LE-LABEL: test9:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 12
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test9:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 12
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr