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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-03-27 02:40:14 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-03-27 02:40:14 +0000 |
| commit | a1b72d0f6a6b3db28cbec2500112d1914bae9662 (patch) | |
| tree | 6ed9026a51f5d0db81d881f31106c2285579080a /llvm/test/CodeGen/PowerPC/tls.ll | |
| parent | d00294483e77932bf5b9cf46262759554373ef79 (diff) | |
| download | bcm5719-llvm-a1b72d0f6a6b3db28cbec2500112d1914bae9662.tar.gz bcm5719-llvm-a1b72d0f6a6b3db28cbec2500112d1914bae9662.zip | |
Remove the link register from the GPR classes on PowerPC.
Some implementation detail in the forgotten past required the link
register to be placed in the GPRC and G8RC register classes. This is
just wrong on the face of it, and causes several extra intersection
register classes to be generated. I found this was having evil
effects on instruction scheduling, by causing the wrong register class
to be consulted for register pressure decisions.
No code generation changes are expected, other than some minor changes
in instruction order. Seven tests in the test bucket required minor
tweaks to adjust to the new normal.
llvm-svn: 178114
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/tls.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/tls.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/PowerPC/tls.ll b/llvm/test/CodeGen/PowerPC/tls.ll index 151b4b7ddab..2daa60ab37f 100644 --- a/llvm/test/CodeGen/PowerPC/tls.ll +++ b/llvm/test/CodeGen/PowerPC/tls.ll @@ -12,7 +12,7 @@ entry: ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT0-NEXT: li [[REG2:[0-9]+]], 42 ;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l -;OPT0-NEXT: stw [[REG2]], 0([[REG1]]) +;OPT0: stw [[REG2]], 0([[REG1]]) ;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT1-NEXT: li [[REG2:[0-9]+]], 42 ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]]) |
