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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-13 15:19:07 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-13 15:19:07 +0000 |
| commit | c752616f30417e277c372ebb32770f62c54b058e (patch) | |
| tree | 74dfbe33cefedb04eddf1b503bfdf49b5efe0860 /llvm/test/CodeGen/PowerPC/tls-cse.ll | |
| parent | 545a0c2fb0886f1c0140ef6cbd05ca0a1c8f800a (diff) | |
| download | bcm5719-llvm-c752616f30417e277c372ebb32770f62c54b058e.tar.gz bcm5719-llvm-c752616f30417e277c372ebb32770f62c54b058e.zip | |
[llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.
Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.
This patch fixes the issue and adds a test to verify that we don't regress that
particular case.
llvm-svn: 330032
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/tls-cse.ll')
0 files changed, 0 insertions, 0 deletions
