[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT

As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314062

1 files changed, 108 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll
new file mode 100644
index 00000000000..106e11bede2
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll
@@ -0,0 +1,108 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 0, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 0, i32* @glob, align 4
+  ret void
+}
+