[DAGCombiner] form 'not' ops ahead of shifts (PR39657)

We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'),
but that would not matter without this patch because DAGCombiner was 
reversing that transform. I think we need this transform in the backend 
regardless of what happens in IR to catch cases where the shift-xor 
is formed late from GEP or other ops.

https://rise4fun.com/Alive/NC1

  Name: shl
  Pre: (-1 << C2) == C1
  %shl = shl i8 %x, C2
  %r = xor i8 %shl, C1
  =>
  %not = xor i8 %x, -1
  %r = shl i8 %not, C2
  
  Name: shr
  Pre: (-1 u>> C2) == C1
  %sh = lshr i8 %x, C2
  %r = xor i8 %sh, C1
  =>
  %not = xor i8 %x, -1
  %r = lshr i8 %not, C2

https://bugs.llvm.org/show_bug.cgi?id=39657

llvm-svn: 347478

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
index 422a2b3f0f2..51ebb5e572d 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -15,8 +15,8 @@ entry:
   ret i64 %conv3
 ; CHECK-LABEL: test_llleus:
 ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
 ; CHECK: blr
 }
 
@@ -67,8 +67,8 @@ entry:
   ret void
 ; CHECK-LABEL: test_llleus_store:
 ; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
+; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
 ; CHECK: blr
 }