[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

This is almost the same as an existing IR canonicalization in instcombine, 
so I'm assuming this is a good early generic DAG combine too.

The motivation comes from reduced bit-hacking for select-of-constants in IR 
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html

The PPC and AArch tests show that those targets are already doing something 
similar. x86 will be neutral in the minimal case and generally better when 
this pattern is extended with other ops as shown in the signbit-shift.ll tests.

Note the asymmetry: we don't include the (extend (ifneg X)) transform because 
it already exists in SimplifySelectCC(), and that is verified in the later 
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the 
general transform to use a shift is always a win because that's a single 
instruction.

Alive proofs:
https://rise4fun.com/Alive/ysli

Name: if pos, get -1
  %c = icmp sgt i16 %x, -1
  %r = sext i1 %c to i16
  =>
  %n = xor i16 %x, -1
  %r = ashr i16 %n, 15

Name: if pos, get 1
  %c = icmp sgt i16 %x, -1
  %r = zext i1 %c to i16
  =>
  %n = xor i16 %x, -1
  %r = lshr i16 %n, 15

Differential Revision: https://reviews.llvm.org/D48970

llvm-svn: 337130

1 files changed, 6 insertions, 6 deletions

diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
index 6fb53977a55..f2096c28ee2 100644
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -39,8 +39,8 @@ entry:
 define i64 @test_llgesll_z(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
@@ -51,8 +51,8 @@ entry:
 define i64 @test_llgesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
@@ -99,9 +99,9 @@ define void @test_llgesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
@@ -115,9 +115,9 @@ define void @test_llgesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    sradi r3, r3, 63
-; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry: