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| author | Hal Finkel <hfinkel@anl.gov> | 2013-11-20 01:10:15 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-11-20 01:10:15 +0000 |
| commit | 22498fa6e3e903863e7a8d02f355651e3269bd6d (patch) | |
| tree | a43fa449271bada8adf371b7640e40369fb209f9 /llvm/test/CodeGen/PowerPC/srl-mask.ll | |
| parent | 8af68f9bdfd5fdab70d4fd5caa8a6e1f17cfafa4 (diff) | |
| download | bcm5719-llvm-22498fa6e3e903863e7a8d02f355651e3269bd6d.tar.gz bcm5719-llvm-22498fa6e3e903863e7a8d02f355651e3269bd6d.zip | |
PPC: Optimize rldicl generation for masked shifts
Masking operations (where only some number of the low bits are being kept) are
selected to rldicl(x, 0, mb). If x is a logical right shift (which would become
rldicl(y, 64-n, n)), we might be able to fold the two instructions together:
rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb) for n <= mb
The right shift is really a left rotate followed by a mask, and if the explicit
mask is a more-restrictive sub-mask of the mask implied by the shift, only one
rldicl is needed.
llvm-svn: 195185
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/srl-mask.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/srl-mask.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/srl-mask.ll b/llvm/test/CodeGen/PowerPC/srl-mask.ll new file mode 100644 index 00000000000..2749df99fd4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/srl-mask.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %x) #0 { +entry: +; CHECK-LABEL: @foo + %a = lshr i64 %x, 35 + %b = and i64 %a, 65535 +; CHECK: rldicl 3, 3, 29, 48 + ret i64 %b +; CHECK: blr +} + +attributes #0 = { nounwind } + |
