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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/PowerPC/split-index-tc.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/split-index-tc.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/split-index-tc.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/split-index-tc.ll b/llvm/test/CodeGen/PowerPC/split-index-tc.ll index 1b27be7cf26..38be93f28a8 100644 --- a/llvm/test/CodeGen/PowerPC/split-index-tc.ll +++ b/llvm/test/CodeGen/PowerPC/split-index-tc.ll @@ -13,7 +13,7 @@ define void @_ZN4llvm17ScheduleDAGInstrs14addPhysRegDepsEPNS_5SUnitEj() #0 align ; CHECK-NOT: lhzu entry: - %0 = load %"class.llvm::MachineOperand"** undef, align 8 + %0 = load %"class.llvm::MachineOperand"*, %"class.llvm::MachineOperand"** undef, align 8 br i1 undef, label %_ZNK4llvm14MachineOperand6getRegEv.exit, label %cond.false.i123 cond.false.i123: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit @@ -22,7 +22,7 @@ cond.false.i123: ; preds = %_ZN4llvm12MachineIn _ZNK4llvm14MachineOperand6getRegEv.exit: ; preds = %_ZN4llvm12MachineInstr10getOperandEj.exit %IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0, i64 undef, i32 1 %1 = bitcast [3 x i8]* %IsDef.i to i24* - %bf.load.i = load i24* %1, align 1 + %bf.load.i = load i24, i24* %1, align 1 %2 = and i24 %bf.load.i, 128 br i1 undef, label %for.cond.cleanup, label %for.body.lr.ph @@ -61,7 +61,7 @@ cond.false.i257: ; preds = %if.end55 unreachable _ZNK4llvm14MachineOperand6isDeadEv.exit262: ; preds = %if.end55 - %bf.load.i259 = load i24* %1, align 1 + %bf.load.i259 = load i24, i24* %1, align 1 br i1 undef, label %if.then57, label %if.else59 if.then57: ; preds = %_ZNK4llvm14MachineOperand6isDeadEv.exit262 |
