[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC

llvm-svn: 336348

1 files changed, 151 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
new file mode 100644
index 00000000000..a64e71bbf74
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
+
+; If positive...
+
+define i32 @zext_ifpos(i32 %x) {
+; CHECK-LABEL: zext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_zext_ifpos(i32 %x) {
+; CHECK-LABEL: add_zext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    addi 3, 3, 41
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_tval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 41
+; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    li 3, 42
+; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifpos(i32 %x) {
+; CHECK-LABEL: sext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  ret i32 %e
+}
+
+define i32 @add_sext_ifpos(i32 %x) {
+; CHECK-LABEL: add_sext_ifpos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    addi 3, 3, 42
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifpos_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifpos_fval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 42
+; CHECK-NEXT:    cmpwi 0, 3, -1
+; CHECK-NEXT:    li 3, 41
+; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    blr
+  %c = icmp sgt i32 %x, -1
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+
+; If negative...
+
+define i32 @zext_ifneg(i32 %x) {
+; CHECK-LABEL: zext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = zext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_zext_ifneg(i32 %x) {
+; CHECK-LABEL: add_zext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    addi 3, 3, 41
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %e = zext i1 %c to i32
+  %r = add i32 %e, 41
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_tval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_tval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 41
+; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    li 3, 42
+; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 42, i32 41
+  ret i32 %r
+}
+
+define i32 @sext_ifneg(i32 %x) {
+; CHECK-LABEL: sext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = sext i1 %c to i32
+  ret i32 %r
+}
+
+define i32 @add_sext_ifneg(i32 %x) {
+; CHECK-LABEL: add_sext_ifneg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    srawi 3, 3, 31
+; CHECK-NEXT:    addi 3, 3, 42
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %e = sext i1 %c to i32
+  %r = add i32 %e, 42
+  ret i32 %r
+}
+
+define i32 @sel_ifneg_fval_bigger(i32 %x) {
+; CHECK-LABEL: sel_ifneg_fval_bigger:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, 42
+; CHECK-NEXT:    cmpwi 0, 3, 0
+; CHECK-NEXT:    li 3, 41
+; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    blr
+  %c = icmp slt i32 %x, 0
+  %r = select i1 %c, i32 41, i32 42
+  ret i32 %r
+}
+