Split the Add, Sub, and Mul instruction opcodes into separate

integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-4.ll b/llvm/test/CodeGen/PowerPC/ppcf128-4.ll
index 8921dfcd5a0..16d61780a46 100644
--- a/llvm/test/CodeGen/PowerPC/ppcf128-4.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcf128-4.ll
@@ -2,9 +2,9 @@
 
 define ppc_fp128 @__floatditf(i64 %u) nounwind  {
 entry:
-        %tmp6 = mul ppc_fp128 0xM00000000000000000000000000000000, 0xM41F00000000000000000000000000000
+        %tmp6 = fmul ppc_fp128 0xM00000000000000000000000000000000, 0xM41F00000000000000000000000000000
         %tmp78 = trunc i64 %u to i32
         %tmp789 = uitofp i32 %tmp78 to ppc_fp128
-        %tmp11 = add ppc_fp128 %tmp789, %tmp6
+        %tmp11 = fadd ppc_fp128 %tmp789, %tmp6
         ret ppc_fp128 %tmp11
 }