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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2016-02-03 17:52:29 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2016-02-03 17:52:29 +0000 |
| commit | ac29f01788e381b2a8560536997d44dfee87086d (patch) | |
| tree | 562248e66a12220a0606717e019c7731a87f13ae /llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll | |
| parent | ae2556f7ee8937926c66f43cfd789bfc2dee2a97 (diff) | |
| download | bcm5719-llvm-ac29f01788e381b2a8560536997d44dfee87086d.tar.gz bcm5719-llvm-ac29f01788e381b2a8560536997d44dfee87086d.zip | |
[ScheduleDAGInstrs::buildSchedGraph()] Handling of memory dependecies rewritten.
Recommited, after some fixing with test cases.
Updated test cases:
test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
test/CodeGen/AArch64/tailcall_misched_graph.ll
Temporarily disabled test cases:
test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
test/CodeGen/PowerPC/ppc64-fastcc.ll (partially updated)
test/CodeGen/PowerPC/vsx-fma-m.ll
test/CodeGen/PowerPC/vsx-fma-sp.ll
http://reviews.llvm.org/D8705
Reviewers: Hal Finkel, Andy Trick.
llvm-svn: 259673
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll b/llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll index 69e15d104da..76677ecdf03 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-fastcc.ll @@ -1,4 +1,6 @@ ; RUN: llc -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s +; XFAIL: * + target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -522,7 +524,7 @@ define void @cv13(<4 x i32> %v) #0 { ; CHECK-LABEL: @cv13 ; CHECK-DAG: li [[REG1:[0-9]+]], 96 -; CHECK-DAG: vor [[REG2:[0-9]+]], 2, 2 +; CHECK-DAG: vor [[REG2:[0-9]+]], 3, 3 ; CHECK: stvx [[REG2]], 1, [[REG1]] ; CHECK: blr } @@ -533,7 +535,7 @@ define void @cv14(<4 x i32> %v) #0 { ; CHECK-LABEL: @cv14 ; CHECK-DAG: li [[REG1:[0-9]+]], 128 -; CHECK-DAG: vor [[REG2:[0-9]+]], 2, 2 +; CHECK-DAG: vor [[REG2:[0-9]+]], 3, 3 ; CHECK: stvx [[REG2]], 1, [[REG1]] ; CHECK: blr } |
