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authorKit Barton <kbarton@ca.ibm.com>2015-11-16 20:22:15 +0000
committerKit Barton <kbarton@ca.ibm.com>2015-11-16 20:22:15 +0000
commit9c432ae111bedfbd7987bfd6824d205cca3dc3e8 (patch)
treecc734f3753c3116cae7286518dc02d92bd28a3bb /llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
parent5a786ddf4c69b3f24620fc2313febc290745740a (diff)
downloadbcm5719-llvm-9c432ae111bedfbd7987bfd6824d205cca3dc3e8.tar.gz
bcm5719-llvm-9c432ae111bedfbd7987bfd6824d205cca3dc3e8.zip
Find available scratch register to use in function prologue and epilogue as part of shrink wrapping.
Phabricator: http://reviews.llvm.org/D13955 llvm-svn: 253247
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll')
-rw-r--r--llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll30
1 files changed, 15 insertions, 15 deletions
diff --git a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
index 9ce302d12c8..a23888425bf 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
@@ -47,7 +47,7 @@
;
; Without shrink-wrapping, epilogue is in the exit block.
; Epilogue code. (What we pop does not matter.)
-; DISABLE: mtlr 0
+; DISABLE: mtlr {{[0-9]+}}
; DISABLE-NEXT: blr
;
@@ -81,7 +81,7 @@ declare i32 @doSomething(i32, i32*)
;
; Prologue code.
; Make sure we save the link register
-; CHECK: mflr 0
+; CHECK: mflr {{[0-9]+}}
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
@@ -110,7 +110,7 @@ declare i32 @doSomething(i32, i32*)
; DISABLE: .[[EPILOG_BB]]: # %if.end
;
; Epilogue code.
-; CHECK: mtlr 0
+; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr
;
; ENABLE: .[[ELSE_LABEL]]: # %if.else
@@ -155,7 +155,7 @@ declare i32 @something(...)
; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
; Prologue code.
; Make sure we save the link register before the call
-; CHECK: mflr 0
+; CHECK: mflr {{[0-9]+}}
;
; Loop preheader
; CHECK-DAG: li [[SUM:[0-9]+]], 0
@@ -171,7 +171,7 @@ declare i32 @something(...)
;
; Next BB
; CHECK: %for.exit
-; CHECK: mtlr 0
+; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr
define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
entry:
@@ -208,7 +208,7 @@ for.end: ; preds = %for.body
;
; Prologue code.
; Make sure we save the link register
-; CHECK: mflr 0
+; CHECK: mflr {{[0-9]+}}
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
@@ -238,7 +238,7 @@ for.end: ; preds = %for.body
;
; DISABLE: .[[EPILOG_BB]]: # %if.end
; Epilog code
-; CHECK: mtlr 0
+; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr
;
; ENABLE: .[[ELSE_LABEL]]: # %if.else
@@ -288,7 +288,7 @@ declare void @somethingElse(...)
;
; Prologue code.
; Make sure we save the link register
-; CHECK: mflr 0
+; CHECK: mflr {{[0-9]+}}
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
@@ -318,7 +318,7 @@ declare void @somethingElse(...)
; DISABLE: .[[EPILOG_BB]]: # %if.end
;
; Epilogue code.
-; CHECK: mtlr 0
+; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr
;
; ENABLE: .[[ELSE_LABEL]]: # %if.else
@@ -439,7 +439,7 @@ if.end: ; preds = %for.body, %if.else
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
-; CHECK: mflr 0
+; CHECK: mflr {{[0-9]+}}
;
; DISABLE: cmplwi 0, 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
@@ -455,7 +455,7 @@ if.end: ; preds = %for.body, %if.else
; CHECK: slwi 3, 3, 3
; DISABLE: b .[[EPILOGUE_BB:LBB[0-9_]+]]
;
-; ENABLE: mtlr 0
+; ENABLE: mtlr {{[0-9]+}}
; ENABLE-NEXT: blr
;
; CHECK: .[[ELSE_LABEL]]: # %if.else
@@ -492,23 +492,23 @@ declare i32 @someVariadicFunc(i32, ...)
; and it hurts the binary size.
;
; CHECK-LABEL: noreturn:
-; DISABLE: mflr 0
+; DISABLE: mflr {{[0-9]+}}
;
; CHECK: cmplwi 3, 0
; CHECK-NEXT: bne 0, .[[ABORT:LBB[0-9_]+]]
;
; CHECK: li 3, 42
;
-; DISABLE: mtlr 0
+; DISABLE: mtlr {{[0-9]+}}
;
; CHECK-NEXT: blr
;
; CHECK: .[[ABORT]]: # %if.abort
;
-; ENABLE: mflr 0
+; ENABLE: mflr {{[0-9]+}}
;
; CHECK: bl abort
-; ENABLE-NOT: mtlr 0
+; ENABLE-NOT: mtlr {{[0-9]+}}
define i32 @noreturn(i8 signext %bad_thing) {
entry:
%tobool = icmp eq i8 %bad_thing, 0
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