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| author | Craig Topper <craig.topper@intel.com> | 2018-01-09 00:50:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-09 00:50:42 +0000 |
| commit | 7c2abdd249b9c7361ff95ee1e90cc46ce2c326d1 (patch) | |
| tree | 7a9103a5aaddf7171a74d94bc25e25b02656d1dd /llvm/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll | |
| parent | 3291e7353e586662cd2df534a80702ea7ccb1437 (diff) | |
| download | bcm5719-llvm-7c2abdd249b9c7361ff95ee1e90cc46ce2c326d1.tar.gz bcm5719-llvm-7c2abdd249b9c7361ff95ee1e90cc46ce2c326d1.zip | |
[X86] Remove unnecessary isel pattern that is a combination of two other patterns.
The pattern was this
def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))),
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit))>, Requires<[NoDQI]>;
but if you just let (i32 (zext X)) match byte itself you'll get MOVZX32rr8. And if you let (i8 (bitconvert (v8i1 VK8:$src))) match by itself you'll get (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit).
So we can just let isel do the two patterns naturally.
llvm-svn: 322049
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll')
0 files changed, 0 insertions, 0 deletions
