[PowerPC] Manually schedule the prologue and epilogue

This patch makes the following changes to the schedule of instructions in the
prologue and epilogue.

The stack pointer update is moved down in the prologue so that the callee saves
do not have to wait for the update to happen.
Saving the lr is moved down in the prologue to hide the latency of the mflr.
The stack pointer is moved up in the epilogue so that restoring of the lr can
happen sooner.
The mtlr is moved up in the epilogue so that it is away form the blr at the end
of the epilogue. The latency of the mtlr can now be hidden by the loads of the
callee saved registers.

Differential Revision: https://reviews.llvm.org/D41737

llvm-svn: 322036

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll b/llvm/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll
index 87b45beeab7..dce8b3ac5b8 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll
@@ -16,12 +16,12 @@ entry:
 ; stfd 14, 416(1)
 
 ; After the fix by patch D34337:
+; CHECK-LE:std 15, -280(1)
+; CHECK-LE:stfd 14, -144(1)
 ; CHECK-LE: stdu 1, -528(1)
-; CHECK-LE:std 15, 248(1)
-; CHECK-LE:stfd 14, 384(1)
+; CHECK-BE:std 15, -280(1)
+; CHECK-BE:stfd 14, -144(1)
 ; CHECK-BE: stdu 1, -544(1)
-; CHECK-BE:std 15, 264(1)
-; CHECK-BE:stfd 14, 400(1)
 }
 
 define signext i32 @foo() {