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| author | Tony Jiang <jtony@ca.ibm.com> | 2017-01-16 14:43:12 +0000 |
|---|---|---|
| committer | Tony Jiang <jtony@ca.ibm.com> | 2017-01-16 14:43:12 +0000 |
| commit | 7630b8c5ee3109986a013b71f7b9352b23101aad (patch) | |
| tree | d53d8765f72a5b78d758fb3e854834d3a6213f34 /llvm/test/CodeGen/PowerPC/p8-isel-sched.ll | |
| parent | f2b135ac3ae26d353c113c10359e6e839ad4845e (diff) | |
| download | bcm5719-llvm-7630b8c5ee3109986a013b71f7b9352b23101aad.tar.gz bcm5719-llvm-7630b8c5ee3109986a013b71f7b9352b23101aad.zip | |
[PowerPC] Expand ISEL instruction into if-then-else sequence.
Generally, the ISEL is expanded into if-then-else sequence, in some
cases (like when the destination register is the same with the true
or false value register), it may just be expanded into just the if
or else sequence.
llvm-svn: 292128
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/p8-isel-sched.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/p8-isel-sched.ll | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll b/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll index 6fa5616dd42..b45a123f027 100644 --- a/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll +++ b/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -24,10 +25,20 @@ entry: ; Make sure that we don't schedule all of the isels together, they should be ; intermixed with the adds because each isel starts a new dispatch group. ; CHECK-LABEL: @foo +; CHECK-NO-ISEL-LABEL: @foo ; CHECK: isel +; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] +; CHECK-NO-ISEL: ori 7, 12, 0 +; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] +; CHECK-NO-ISEL: [[TRUE]] +; CHECK-NO-ISEL-NEXT: addi 7, 11, 0 ; CHECK: addi ; CHECK: isel +; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] +; CHECK-NO-ISEL: ori 10, 11, 0 +; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] +; CHECK-NO-ISEL: [[TRUE]] +; CHECK-NO-ISEL-NEXT: addi 10, 12, 0 ; CHECK: blr attributes #0 = { nounwind } - |
