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| author | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-26 02:12:32 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-26 02:12:32 +0000 |
| commit | 6d88b7d6e712789115c149c5abb0f359d1222545 (patch) | |
| tree | d98ef508266356c4ef90716b3f05a24b1ef5eb0d /llvm/test/CodeGen/PowerPC/machine-pre.ll | |
| parent | 6cf6f7dc96d55af63a15fb73499bf81d00f969b3 (diff) | |
| download | bcm5719-llvm-6d88b7d6e712789115c149c5abb0f359d1222545.tar.gz bcm5719-llvm-6d88b7d6e712789115c149c5abb0f359d1222545.zip | |
[PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Summary:
If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't
have match pattern, so their hasSideEffects flag will be set true by
`llvm-tblgen`.
But in fact, we can use `[LR]` to model the two instructions, so they should not
have SideEffects.
This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D71390
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/machine-pre.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/machine-pre.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/PowerPC/machine-pre.ll b/llvm/test/CodeGen/PowerPC/machine-pre.ll index cc6d738bfc7..0a794972572 100644 --- a/llvm/test/CodeGen/PowerPC/machine-pre.ll +++ b/llvm/test/CodeGen/PowerPC/machine-pre.ll @@ -134,10 +134,10 @@ define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) nounwind { ; CHECK-P9-NEXT: .LBB1_10: # %cleanup20 ; CHECK-P9-NEXT: addi r1, r1, 80 ; CHECK-P9-NEXT: ld r0, 16(r1) -; CHECK-P9-NEXT: mtlr r0 ; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; CHECK-P9-NEXT: mtlr r0 ; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: blr entry: |
