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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-04 06:59:23 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-04 06:59:23 +0000 |
| commit | 11049f8f07330c30c689d54ed91d63909b360cf2 (patch) | |
| tree | a70b349635cb8c9c5d445cc77595f2794e5e0dc4 /llvm/test/CodeGen/PowerPC/machine-combiner.ll | |
| parent | 6b929d5ba91eec2acd6f47c6921ce0dff9a94cd6 (diff) | |
| download | bcm5719-llvm-11049f8f07330c30c689d54ed91d63909b360cf2.tar.gz bcm5719-llvm-11049f8f07330c30c689d54ed91d63909b360cf2.zip | |
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
This patch corresponds to review:
https://reviews.llvm.org/D23155
This patch removes the VSHRC register class (based on D20310) and adds
exploitation of the Power9 sub-word integer loads into VSX registers as well
as vector sign extensions.
The new instructions are useful for a few purposes:
Int to Fp conversions of 1 or 2-byte values loaded from memory
Building vectors of 1 or 2-byte integers with values loaded from memory
Storing individual 1 or 2-byte elements from integer vectors
This patch implements all of those uses.
llvm-svn: 283190
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/machine-combiner.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/machine-combiner.ll | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/PowerPC/machine-combiner.ll b/llvm/test/CodeGen/PowerPC/machine-combiner.ll index 5e097b61b78..e026017710e 100644 --- a/llvm/test/CodeGen/PowerPC/machine-combiner.ll +++ b/llvm/test/CodeGen/PowerPC/machine-combiner.ll @@ -98,7 +98,6 @@ define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, < ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] -; CHECK-PWR: # kill ; CHECK-NEXT: blr %t0 = fadd <4 x float> %x0, %x1 @@ -116,7 +115,6 @@ define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, < ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] -; CHECK-PWR: # kill ; CHECK-NEXT: blr %t0 = fadd <4 x float> %x0, %x1 @@ -134,7 +132,6 @@ define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, < ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] -; CHECK-PWR: # kill ; CHECK-NEXT: blr %t0 = fadd <4 x float> %x0, %x1 @@ -152,7 +149,6 @@ define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, < ; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35 ; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37 ; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]] -; CHECK-PWR: # kill ; CHECK-NEXT: blr %t0 = fadd <4 x float> %x0, %x1 |
