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| author | Jinsong Ji <jji@us.ibm.com> | 2019-08-29 21:53:59 +0000 |
|---|---|---|
| committer | Jinsong Ji <jji@us.ibm.com> | 2019-08-29 21:53:59 +0000 |
| commit | 1ed7d2119ee2bb5b7cc1368d739b13f5ce0692da (patch) | |
| tree | 5fe222784da166e4de49bdeddacdd6de3a13538a /llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll | |
| parent | 04e657be2875f981811e5df4d294a06f7190422d (diff) | |
| download | bcm5719-llvm-1ed7d2119ee2bb5b7cc1368d739b13f5ce0692da.tar.gz bcm5719-llvm-1ed7d2119ee2bb5b7cc1368d739b13f5ce0692da.zip | |
[PowerPC] Support extended mnemonics mffprwz etc.
Summary:
Reported in https://github.com/opencv/opencv/issues/15413.
We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions
eg: mffprd,mtfprd etc.
We only support one of them, this patch add the others.
Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc
Reviewed By: hfinkel
Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66963
llvm-svn: 370411
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll b/llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll new file mode 100644 index 00000000000..81eba8238b9 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/inlineasm-extendedmne.ll @@ -0,0 +1,72 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \ +; RUN: -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s + +define dso_local void @foo() { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: #APP +; CHECK-NEXT: mfvsrd r0, vs33 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mffprd r0, f3 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mfvsrd r0, vs34 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mfvsrwz r0, vs33 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mffprwz r0, f3 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mfvsrwz r0, vs34 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtvsrd vs33, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtfprd f3, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtvsrd vs34, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtvsrwa vs33, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtfprwa f3, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtvsrwa vs34, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtvsrwz vs33, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtfprwz f3, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: #APP +; CHECK-NEXT: mtvsrwz vs34, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: blr +entry: + call void asm sideeffect "mfvsrd 0,33", ""() + call void asm sideeffect "mffprd 0,3", ""() + call void asm sideeffect "mfvrd 0,2", ""() + call void asm sideeffect "mfvsrwz 0,33", ""() + call void asm sideeffect "mffprwz 0,3", ""() + call void asm sideeffect "mfvrwz 0,2", ""() + call void asm sideeffect "mtvsrd 33,0", ""() + call void asm sideeffect "mtfprd 3,0", ""() + call void asm sideeffect "mtvrd 2,0", ""() + call void asm sideeffect "mtvsrwa 33,0", ""() + call void asm sideeffect "mtfprwa 3,0", ""() + call void asm sideeffect "mtvrwa 2,0", ""() + call void asm sideeffect "mtvsrwz 33,0", ""() + call void asm sideeffect "mtfprwz 3,0", ""() + call void asm sideeffect "mtvrwz 2,0", ""() + ret void +} + |
