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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2015-08-13 17:40:44 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2015-08-13 17:40:44 +0000 |
| commit | 1c39ca6501a5c9259a166a03fceb049d886cbea4 (patch) | |
| tree | 079e93a1f6cd2b943ab0f2848dc1833073630fde /llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll | |
| parent | 30143aee112770247554b8c371ea03998300667d (diff) | |
| download | bcm5719-llvm-1c39ca6501a5c9259a166a03fceb049d886cbea4.tar.gz bcm5719-llvm-1c39ca6501a5c9259a166a03fceb049d886cbea4.zip | |
Scalar to vector conversions using direct moves
This patch corresponds to review:
http://reviews.llvm.org/D11471
It improves the code generated for converting a scalar to a vector value. With
direct moves from GPRs to VSRs, we no longer require expensive stack operations
for this. Subsequent patches will handle the reverse case and more general
operations between vectors and their scalar elements.
llvm-svn: 244921
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll index 1d9b6482314..4868a18a95a 100644 --- a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll +++ b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll @@ -24,8 +24,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfcc ; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG01]] +; CHECK: xscvuxdsp 1, [[MOVEREG01]] } ; Function Attrs: nounwind @@ -77,8 +76,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfuch ; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG03]] +; CHECK: xscvuxdsp 1, [[MOVEREG03]] } ; Function Attrs: nounwind @@ -130,8 +128,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfss ; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG05]] +; CHECK: xscvsxdsp 1, [[MOVEREG05]] } ; Function Attrs: nounwind @@ -183,8 +180,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfust ; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG07]] +; CHECK: xscvuxdsp 1, [[MOVEREG07]] } ; Function Attrs: nounwind @@ -236,8 +232,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfii ; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG09]] +; CHECK: xscvsxdsp 1, [[MOVEREG09]] } ; Function Attrs: nounwind @@ -289,8 +284,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfuij ; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG11]] +; CHECK: xscvuxdsp 1, [[MOVEREG11]] } ; Function Attrs: nounwind @@ -342,8 +336,7 @@ entry: ret float %conv ; CHECK-LABEL:@_Z7testfllx ; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG13]] +; CHECK: xscvsxdsp 1, [[MOVEREG13]] } ; Function Attrs: nounwind @@ -395,8 +388,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z8testfully ; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG15]] +; CHECK: xscvuxdsp 1, [[MOVEREG15]] } ; Function Attrs: nounwind |
